Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: Provided is a device with a replacement spacer structure and a method for forming such a structure. The method includes forming an initial spacer structure, wherein the initial spacer structure has an initial etch rate for a selected etchant. The method further includes removing a portion of the initial spacer structure, wherein a remaining portion of the initial spacer structure is not removed. Also, the method includes forming a replacement spacer structure adjacent to the remaining portion of the initial spacer structure to form a combined spacer structure, wherein the combined spacer structure has an intermediate etch rate for the selected etchant that is less than the initial etch rate for a selected etchant. Further, the method includes etching the combined spacer structure with the selected etchant to form a final spacer structure.

Abstract: An exogenous biomolecular tracing method includes: extracting a nucleotide marker from a marker source organism; combining a basic material with the nucleotide marker to form a nucleotide marked material; exogenously combining an aquatic creature or an aquatic product to form an exogenously-marked aquatic creature or an exogenously-marked aquatic product; and identifying a DNA sample from the exogenously-marked aquatic creature or the exogenously-marked aquatic product with at least one primer pair in an exogenous biomolecular tracing procedure to obtain an exogenously-marked identification result.

Abstract: A biomolecular characteristic identification method includes: breeding a plurality of Taiwan Tilapias in a predetermined environment to obtain a plurality of baited Taiwan Tilapias; seeking at least one nucleotide mark in the baited Taiwan Tilapias to obtain at least one feature sequence marker therefrom; producing at least one design of primer pair according to the feature sequence marker for identification; and identifying an unknown DNA sample of the baited Taiwan Tilapias with the at least one primer pair in a biomolecular tracing procedure to obtain an identification result.

Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.

Abstract: Disclosed is a method and system for achieving optimal separable convolutions, the method is applied to image analyzing and processing and comprises steps of: inputting an image to be analyzed and processed; calculating three sets of parameters of a separable convolution: an internal number of groups, a channel size and a kernel size of each separated convolution, and achieving optimal separable convolution process; and performing deep neural network image process. The method and system in the present disclosure adopts implementation of separable convolution which efficiently reduces a computational complexity of deep neural network process. Comparing to the FFT and low rank approximation approaches, the method and system disclosed in the present disclosure is efficient for both small and large kernel sizes and shall not require a pre-trained model to operate on and can be deployed to applications where resources are highly constrained.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Abstract: An immersion cooling equipment includes an immersion cooling device, a heating component and a cooling liquid. The immersion cooling device includes a tank providing cooling by immersion and a liquid supply equipment. The tank providing cooling by immersion communicates with the liquid supply equipment and accommodates the heating component and the cooling liquid. The tank providing cooling by immersion includes a mounting bracket, a cooling box, and a sealing plate. The cooling box is positioned in the mounting bracket, the cooling box comprising a plurality of walls, the plurality of walls surround a reception space, the reception space comprising a first opening. The sealing plate is detachably connected or rotatably connected the cooling box, and is used to close or reveal the first opening. Each the walls is made of thermoplastic plastic, and any two abutting walls are fixed by plastic welding.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A method according to the present disclosure includes receiving a workpiece that includes a first source/drain feature, a first dielectric layer over the first source/drain feature, and a source/drain contact disposed in the first dielectric layer and over the first source/drain feature. The method further includes depositing a second dielectric layer over the source/drain contact and the first dielectric layer, forming a source/drain contact via opening through the second dielectric layer to expose the source/drain contact, depositing a sacrificial plug in the source/drain contact via opening, depositing a third dielectric layer over the second dielectric layer and the sacrificial plug, forming a trench in the third dielectric layer to expose the sacrificial plug, removing the sacrificial plug to expose the source/drain contact via opening, and after the removing of the sacrificial plug, forming an integrated conductive feature into the trench and the exposed source/drain contact via opening.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.