Patents by Inventor Chang Wen

Chang Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dielectric Spacer to Prevent Contacting Shorting
    Publication number: 20200013875
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
  • SRAM STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20200006354
    Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.
    Type: Application
    Filed: April 5, 2019
    Publication date: January 2, 2020
    Inventors: MING-CHANG WEN, KUO-HSIU HSU, JYUN-YU TIAN, WAN-YAO WU, CHANG-YUN CHANG, HUNG-KAI CHEN, LIEN JUNG HUNG
  • Dielectric Spacer to Prevent Contacting Shorting
    Publication number: 20190393324
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu
  • Package structure and method of manufacturing the same
    Patent number: 10504865
    Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Creating devices with multiple threshold voltage by cut-metal-gate process
    Patent number: 10461078
    Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
  • Cut Metal Gate Process for Reducing Transistor Spacing
    Publication number: 20190318922
    Abstract: A semiconductor structure includes a substrate; first and second fins extending from the substrate and oriented lengthwise generally along a first direction; an isolation feature over the substrate and separating bottom portions of the first and the second fins; first and second epitaxial semiconductor features over the first and the second fins, respectively; and a first dielectric feature sandwiched between the first and the second epitaxial semiconductor features. A maximum width of the first dielectric feature is smaller than a width of the isolation feature between the first and the second fins along a second direction perpendicular to the first direction.
    Type: Application
    Filed: May 24, 2019
    Publication date: October 17, 2019
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • MANUFACTURING METHOD OF VAMP WITH EMBOSSED PATTERN AND MANUFACTURING SYSTEM THEREOF
    Publication number: 20190307210
    Abstract: The present disclosure illustrates a manufacturing method of a vamp with an embossed pattern comprising: (1) providing a plain cloth. (2) heating the plain cloth by an oven to soften the plain cloth. (3) cooling the plain cloth and forming an embossed pattern on the plain cloth by a cold pressing roller, and the cold pressing roller provided with a predetermined pattern. (4) forming an embossed layer with the embossed pattern on the plain cloth. Because of the cold pressing roller, a depth of the cooled embossed layer is the same as a depth of the predetermined pattern. Hence, the embossed pattern can maintain its appearance.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Inventors: Wen-Tsao WEN, Yu-Chang WEN
  • Spatial scalable video multicast for heterogeneous MIMO systems
    Patent number: 10432270
    Abstract: A multiplexed space-time block coding (M-STBC) scheme is described that allows for transmitting a single multicast transmission in a heterogeneous MIMO (i.e., multiple-input and multiple-output) environment, where receivers with fewer antennas can receive a lower resolution version of the multi-cast transmission, while receivers with a greater number of antennas can receive a higher resolution version of the multi-cast transmission. Thus, the M-STBC scheme allows for transmitting the single multicast transmission that includes both a spatial multiplexing mode and a diversity mode.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 1, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chong Luo, Hao Cui, Chang Wen Chen, Feng Wu
  • Creating Devices with Multiple Threshold Voltage by Cut-Metal-Gate Process
    Publication number: 20190267372
    Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 29, 2019
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
  • Cut metal gate process for reducing transistor spacing
    Patent number: 10319581
    Abstract: A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Cut Metal Gate Process for Reducing Transistor Spacing
    Publication number: 20190164741
    Abstract: A method includes providing a structure having a substrate and first and second fins over the substrate and oriented lengthwise generally along a first direction; epitaxially growing semiconductor source/drain (S/D) features over the first and second fins, wherein a first semiconductor S/D feature over the first fin merges with a second semiconductor S/D feature over the second fin; and performing a first etching process to an area between the first and second fins, wherein the first etching process separates the first and second semiconductor S/D features.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
    Publication number: 20190164838
    Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.
    Type: Application
    Filed: February 9, 2018
    Publication date: May 30, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun CHANG, Bone-Fong WU, Ming-Chang WEN, Ya-Hsiu LIN
  • Etch Stop Layer Between Substrate and Isolation Structure
    Publication number: 20190157159
    Abstract: A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Method for manufacturing semiconductor device
    Patent number: 10290543
    Abstract: A method for manufacturing semiconductor device is provided. A substrate having a memory region and a capacitance region is provided. A plurality of word line structures are formed on the memory region of the substrate. A capacitance structure is formed on the capacitance region of the substrate. The word line structures and the capacitance structure each include a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer. The second conductive layers of the word line structures close to an edge of the memory region and a portion of the second conductive layer of the capacitance structure are removed at the same time to form a trench exposing a portion of the second dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 14, 2019
    Assignee: MACRONXI International Co., Ltd.
    Inventors: Chang-Wen Jian, Hsiang-Lu Wu, Yu-Min Hung, Tzung-Ting Han
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190096841
    Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Method of dyeing knitted fabrics, and fabric and vamp fabric with predetermined color using the same
    Patent number: 10214854
    Abstract: A method of dyeing knitted fabrics and fabric and vamp fabric with predetermined color using the same are provided. The method includes steps of: providing a plain knitted fabric; entirely spray dyeing the fabric by dye liquor containing nano-particles through the printing and spraying process; executing a high temperature process or a steam process of a thermally drying process to the dyed knitted fabric so that the nano-particles can attach into the fabric of the knitted fabric, and forming the knitted fabric with the predetermined color after the knitted fabric is dyed. The fabric and the dyeing method provided can therefore reduce the production of sewage effectively.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 26, 2019
    Assignee: LONG JOHN TSUNG RIGHT INDUSTRIAL CO., LTD.
    Inventors: Wen-Tsao Wen, Yu-Chang Wen
  • Display apparatus of multi-color light sources and driving method thereof
    Patent number: 10204572
    Abstract: A display apparatus including a plurality of pixels and a multi-color light source backlight module, and a driving method thereof are disclosed. Each pixel includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a white sub-pixel. The backlight module includes a first color light source, a second color light source, and a third color light source. In a first sub-frame period, the first color light source and the second color light source are lightening; in a second sub-frame period, the second color light source and the third color light source are lightening; and in a third sub-frame period, the first color light source and the third color light source are lightening.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 12, 2019
    Assignee: AU OPTRONICS CORP.
    Inventors: Seok-Lyul Lee, Yu-Chang Wen
  • Structure and method for overlay marks
    Patent number: 10163738
    Abstract: A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Ming-Chang Wen, Chun-Kuang Chen, Yao-Ching Ku
  • RECYCLED FABRIC STRUCTURE, KNITTED VAMP CLOTH AND METHOD OF MANUFACTURING YARN
    Publication number: 20180305847
    Abstract: A recycled fabric structure is provided, which includes a plurality of types of blended yarn arranged by weaving or interlacing. Wherein, each of the types of the blended yarn has a plurality of first fibers and a plurality of second fibers vertically arranged and interloped with each other. The plurality of first fibers accounts for 30% to 50% of the total weight of the blended yarn. The first fiber is a recycled fiber.
    Type: Application
    Filed: February 11, 2018
    Publication date: October 25, 2018
    Inventors: WEN-TSAO WEN, Yu-Chang Wen
  • ZIP FASTENER WITH AUGMENTED INDICATION
    Publication number: 20180078005
    Abstract: A zip fastener consisting of two zipper tapes, two series of interlocking teeth and a zipper slider is disclosed. Each interlocking tooth includes a front engagement end piece and a rear extension end piece respectively extended from a tooth body thereof in reversed direction. The rear extension end piece provides a track for supporting and guiding sliding movement of the zipper slider and an augmented portion that exhibits a visual indication.
    Type: Application
    Filed: August 27, 2017
    Publication date: March 22, 2018
    Inventor: Chang-Wen TSAO