Patents by Inventor Chang-Woo Oh

Chang-Woo Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100012990
    Abstract: A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Inventors: MIN-SANG KIM, CHANG-WOO OH, DONG-WON KIM, KYOUNG-HWAN YEO, SUNG-MIN KIM
  • Patent number: 7618864
    Abstract: Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: November 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-woo Oh, Sung-hwan Kim, Dong-gun Park, Dong-won Kim
  • Patent number: 7605025
    Abstract: A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-sang Kim, Chang-woo Oh, Dong-won Kim, Kyoung-hwan Yeo, Sung-min Kim
  • Patent number: 7601592
    Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Patent number: 7575964
    Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Jeong-Dong Choe, Kyoung-Hwan Yeo
  • Publication number: 20090203178
    Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.
    Type: Application
    Filed: April 9, 2009
    Publication date: August 13, 2009
    Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
  • Patent number: 7541645
    Abstract: A unit cell of a metal oxide semiconductor (MOS) transistor is provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. First and second spaced apart buffer regions are provided beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-Gun Park, Sung-Young Lee, Hye-Jin Cho, Eun-Jung Yun, Shin-Ae Lee, Chang-Woo Oh, Jeong-Dong Choe
  • Patent number: 7535051
    Abstract: A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Na-Young Kim, Chang-Woo Oh, Sung-Hwan Kim, Yong-Lack Choi
  • Patent number: 7510932
    Abstract: A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: March 31, 2009
    Assignee: SAms Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Jeong-Dong Choe
  • Publication number: 20090065850
    Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
    Type: Application
    Filed: November 6, 2008
    Publication date: March 12, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Publication number: 20090035903
    Abstract: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 5, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Ki-Whan Song
  • Publication number: 20090001503
    Abstract: A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.
    Type: Application
    Filed: June 25, 2008
    Publication date: January 1, 2009
    Inventors: Chang-Woo Oh, Dong-Gun Park
  • Publication number: 20080296638
    Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of the protrusion being sharp and defining a first active region of the active pattern along a first direction, isolation layer patterns on the substrate in recesses at both sides of the active pattern, the isolation layer patterns exposing the first active region, a gate structure on the first active region and on the isolation layer patterns, the gate structure extending along a second direction, the first and second directions being perpendicular to each other, and source/drain regions under the first active region at both sides of the gate structure.
    Type: Application
    Filed: May 22, 2008
    Publication date: December 4, 2008
    Inventors: Chang-Woo Oh, Sung-In Hong, Dong-Gun Park
  • Publication number: 20080296649
    Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.
    Type: Application
    Filed: November 21, 2007
    Publication date: December 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo OH, Dong-Gun PARK, Jeong-Dong CHOE, Kyoung-Hwan YEO
  • Publication number: 20080283879
    Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.
    Type: Application
    Filed: July 30, 2008
    Publication date: November 20, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-yong Choi, Chang-woo Oh, Dong-gun Park, Dong-won Kim
  • Patent number: 7442988
    Abstract: Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Oh, Ki-Whan Song
  • Publication number: 20080242075
    Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
    Type: Application
    Filed: June 9, 2008
    Publication date: October 2, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Yong-Kyu Lee
  • Publication number: 20080237641
    Abstract: An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed.
    Type: Application
    Filed: June 11, 2008
    Publication date: October 2, 2008
    Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Sung-Young Lee
  • Publication number: 20080224206
    Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.
    Type: Application
    Filed: April 21, 2008
    Publication date: September 18, 2008
    Inventors: Chang-Woo Oh, Dong-Gun Park, Sung-Young Lee, Chang-Sub Lee, Jeong-Dong Choe
  • Patent number: 7419879
    Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: September 2, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-yong Choi, Chang-woo Oh, Dong-gun Park, Dong-won Kim