Abstract: A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

Abstract: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

Abstract: An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.

Abstract: According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example the first crystalline phase may be a hexagonal closed packed structure and the first crystalline phase may be a face centered cubic structure.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: Phase change memory devices and methods of making phase changeable memory devices including a heating electrode disposed on a substrate are provided. The heating electrode includes an electrode hole in the heating electrode. A phase change material pattern is provided in the electrode hole and contacts a sidewall of the electrode hole. In some embodiments, the electrode hole extends through the heating electrode. In some embodiments, the phase changeable material pattern only contacts the electrode at a sidewall of the electrode hole.

Abstract: Phase-changeable memory devices include non-volatile memory cells. Each of these non-volatile memory cells may include a phase-changeable diode on a semiconductor substrate and a phase-changeable memory element having a first terminal electrically coupled to a terminal of the phase-changeable diode. This phase-changeable diode may include a lower electrode pattern on the semiconductor substrate, a first phase-changeable pattern on the lower electrode pattern and a gate switching layer pattern on the first phase-changeable pattern. The phase-changeable memory element includes a second phase-changeable pattern electrically coupled to the terminal of the phase-changeable diode and a memory switching layer pattern on the second phase-changeable pattern. The memory switching layer pattern may include a composite of a titanium layer pattern contacting the phase-changeable memory element and a titanium nitride layer pattern contacting the titanium layer pattern.

Abstract: Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.

Abstract: In one embodiment, a phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: In a memory device and in a method of programming the same, a memory device comprises: a plurality of memory cells, each memory cell comprising a resistance-changeable material that has an initial resistance that is determined in response to an applied programming current in a programming operation; and a modification circuit that modifies the resistance of the memory cell following a programming operation of the memory cell to vary the resistance of the memory cell from the initial resistance to a second resistance by applying a saturation current in a saturation operation. Each memory cell is connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation, that is used to apply the saturation current to the corresponding memory cell in the saturation operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a subsequent read operation.

Abstract: In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: Rdrift=Rinitial×t?; where Rdrift represents a final resistance of the memory cell following the time period, Rinitial represents the initial resistance of the memory cell following the programming operation, t represents the time period; and ? represents the drift parameter.

Abstract: A semiconductor memory device includes first conductive lines on a substrate, an interlayer insulating layer with a plurality of via holes on the substrate, second conductive lines on the interlayer insulating layer, and a resistive memory material in the via holes and electrically connected to the first and second conductive lines, the resistive memory material having a vertically non-uniform specific resistance profile with respect to the substrate.

Abstract: A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Abstract: A phase-change random access memory device may include a phase-change pattern, a first electrode structure connected to the phase-change pattern, and a second electrode structure spaced apart from the first electrode structure and connected to the phase-change pattern, wherein at least one of the first electrode structure and the second electrode structure includes a plurality of resistor patterns connected to the phase-change pattern in parallel.

Abstract: A phase-change random access memory (PRAM) device includes a first electrode and a second electrode on a substrate. A phase change pattern is interposed between the first and second electrodes. An interlayer insulating layer having a contact hole is provided on the substrate. The phase change pattern may be disposed in the contact hole. The phase change pattern includes a plurality of doping patterns having different doping concentrations. Methods of forming a multi-bit PRAM device are also disclosed.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation and a method of manufacturing the same. In one embodiment, a semiconductor memory device comprises a molding layer overlying a semiconductor substrate. The molding layer has a protrusion portion vertically extending from a top surface thereof. The device further includes a phase-changeable material pattern adjacent the protrusion portion and a lower electrode electrically connected to the phase-changeable material pattern.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.

Abstract: A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.