Patents by Inventor Changhan Hobie Yun

Changhan Hobie Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250219618
    Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.
    Type: Application
    Filed: March 19, 2025
    Publication date: July 3, 2025
    Inventors: Kai LIU, Rui TANG, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
  • Patent number: 12341488
    Abstract: A package comprising an acoustic device, a polymer frame coupled to the acoustic device, a plurality of frame interconnects located in the polymer frame, where the plurality of frame interconnects are coupled to the acoustic device, a polymer cap layer coupled to the acoustic device though the polymer frame, where the polymer cap layer is configured as a cap for the acoustic device, a plurality of cap interconnects located in the polymer cap layer, where the plurality of cap interconnects are coupled to the plurality of frame interconnects, and a cavity located between the acoustic device and the polymer cap layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: June 24, 2025
    Assignee: QUALCOMM INCORPORATED
    Inventors: Sebastian Brunner, Changhan Hobie Yun, Stefan Leopold Hatzl, Manuel Hofer, Horst Droescher, Christian Hoffmann
  • Publication number: 20250164713
    Abstract: A device includes a glass layer and an optical fiber directly attached to the glass layer. The device also includes a photo diode electrically connected to an antenna element. The device further includes a lens coupled to or included within the glass layer and configured to manipulate light exchanged between the optical fiber and the photo diode. The photo diode is configured to convert optical signals from the optical fiber into electrical signals for the antenna element, convert electrical signals from the antenna element to optical signals provided to the optical fiber, or both.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 22, 2025
    Inventors: Changhan Hobie YUN, Youngju PARK, Doosoub SHIN
  • Patent number: 12273095
    Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 8, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Liu, Rui Tang, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20240321724
    Abstract: A device includes a passive substrate having a first metallization layer on a first surface of the passive substrate. The first metallization layer is composed of a first passive component and a first plate portion. The device includes an insulator layer coupled to the first plate portion of the first metallization layer. The device also includes a first conductive interconnect coupled to the insulator layer to form a second passive component coupled to the first passive component. The device further includes a laminate substrate coupled to the first conductive interconnect.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Doosoub SHIN, Changhan Hobie YUN, Youngju PARK
  • Publication number: 20240297165
    Abstract: A device is described, including a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate, through at least a first pair of conductive pillars. The device also includes a laminate substrate coupled to the first surface of the RDL substrate through at least a second pair of conductive pillars.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 5, 2024
    Inventors: Changhan Hobie YUN, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR, Youngju PARK, Doosoub SHIN
  • Patent number: 12016247
    Abstract: A package that includes an integrated device, an integrated passive device and a void. The integrated device is configured as a filter. The integrated device includes a substrate comprising a piezoelectric material, and at least one metal layer coupled to a first surface of the first substrate. The integrated passive device is coupled to the integrated device. The integrated passive device is configured as a cap for the integrated device. The void is located between the integrated device and the integrated passive device.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 18, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Changhan Hobie Yun, Nosun Park, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Sameer Sunil Vadhavkar
  • Patent number: 12009292
    Abstract: An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: June 11, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Nosun Park, Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Sameer Sunil Vadhavkar
  • Publication number: 20240097648
    Abstract: A package comprising an acoustic device, a polymer frame coupled to the acoustic device, a plurality of frame interconnects located in the polymer frame, where the plurality of frame interconnects are coupled to the acoustic device, a polymer cap layer coupled to the acoustic device though the polymer frame, where the polymer cap layer is configured as a cap for the acoustic device, a plurality of cap interconnects located in the polymer cap layer, where the plurality of cap interconnects are coupled to the plurality of frame interconnects, and a cavity located between the acoustic device and the polymer cap layer. The acoustic device includes a substrate and an acoustic element coupled to the substrate.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Inventors: Sebastian BRUNNER, Changhan Hobie YUN, Stefan Leopold HATZL, Manuel HOFER, Horst DROESCHER, Christian HOFFMANN
  • Publication number: 20230352423
    Abstract: Disclosed is a device that includes a die and a protection layer surrounding the die. The protection layer is applied at a backend process prior to dicing a wafer to individual dies. The protection layer protects the die from chips and cracks during and after dicing the wafer.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Inventors: Sameer Sunil VADHAVKAR, Changhan Hobie YUN, Paragkumar Ajaybhai THADESAR, Nosun PARK, Daniel Daeik KIM
  • Patent number: 11770115
    Abstract: An exemplary tunable circuit includes an inductor coupled to a node and a first capacitor coupled to the node. The tunable circuit also includes a variable capacitor coupled to the node, such that a total capacitance of the tunable circuit depends on a fixed capacitance of the first capacitor and a variable capacitance of the variable capacitor. In an example, the inductor and the first capacitor are both included in a passive device and the variable capacitor is in a semiconductor device. The variable capacitor allows the total capacitance to be modified for the purpose of, for example, calibrating the capacitance to account for manufacturing variations, and/or adjusting to a frequency range of operation used by wireless devices in a region of the world. The first capacitor may be a higher quality capacitor providing a larger portion of the total capacitance than the variable capacitor.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: September 26, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Changhan Hobie Yun, Hannu Laurila, Ville Lehtisalo, Ville Herman Brunou, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Wei Cheng
  • Patent number: 11728293
    Abstract: Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: August 15, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Sameer Sunil Vadhavkar
  • Publication number: 20230230910
    Abstract: A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 20, 2023
    Inventors: Changhan Hobie YUN, Nosun PARK, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR
  • Publication number: 20230187340
    Abstract: An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Inventors: Nosun PARK, Changhan Hobie YUN, Daniel Daeik KIM, Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR
  • Patent number: 11658403
    Abstract: A substrate that includes at least one dielectric layer, a plurality of interconnects, and a curved antenna coupled to a surface of the substrate. The curved antenna is curved relative to the surface of the substrate such that at least part of the curved antenna is offset from the surface of the substrate. The substrate includes a first antenna dielectric layer coupled to the surface of the substrate, an antenna ground interconnect coupled to the first antenna dielectric layer, and a second antenna dielectric layer coupled to the antenna ground interconnect. The antenna ground interconnect configured to be coupled to ground. The curved antenna is coupled to the second antenna dielectric layer.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Changhan Hobie Yun, Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Nosun Park, Sameer Sunil Vadhavkar
  • Patent number: 11626236
    Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 11, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Lan, Ranadeep Dutta
  • Publication number: 20230082743
    Abstract: Disclosed are a device and techniques for fabricating the device. The device may include a top substrate including a plurality of top vias coupled to a first top metal layer that forms a top winding portion of a first inductor. The device also includes a middle substrate including one or more middle metal layers. The top substrate is disposed on the middle substrate. The one or more middle metal layers form a middle winding portion of the first inductor. The device also includes a bottom substrate electrically coupled to the middle substrate opposite the top substrate, where a first bottom metal layer of the bottom substrate forms a bottom winding portion of the first inductor.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Changhan Hobie YUN, Nosun PARK, Paragkumar Ajaybhai THADESAR, Daniel Daeik KIM, Sameer Sunil VADHAVKAR, Vinay PRAKASH
  • Patent number: 11515247
    Abstract: A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: November 29, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Nosun Park, Changhan Hobie Yun, Daniel Daeik Kim, Sameer Sunil Vadhavkar, Paragkumar Ajaybhai Thadesar
  • Patent number: 11502652
    Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Nosun Park
  • Publication number: 20220285080
    Abstract: An inductor includes a first metallization layer multi-turn trace. The inductor also includes a second metallization layer multi-turn trace coupled to the first metallization layer multi-turn trace through at least one first via. The inductor further includes a plurality of discrete third metallization layer trace segments coupled to the second metallization layer multi-turn trace through a plurality of second vias.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 8, 2022
    Inventors: Jonghae KIM, Changhan Hobie YUN, Je-Hsiung LAN, Ranadeep DUTTA