Patents by Inventor Changhan Hobie Yun
Changhan Hobie Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11121699Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.Type: GrantFiled: February 19, 2019Date of Patent: September 14, 2021Assignee: Qualcomm IncorporatedInventors: Kai Liu, Rui Tang, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
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Publication number: 20210257989Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.Type: ApplicationFiled: April 30, 2021Publication date: August 19, 2021Inventors: Kai LIU, Rui TANG, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
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Patent number: 11024454Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.Type: GrantFiled: June 23, 2016Date of Patent: June 1, 2021Assignee: Qualcomm IncorporatedInventors: Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Niranjan Sunil Mudakatte, Jonghae Kim, Chengjie Zuo, David Francis Berdy
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Patent number: 10944379Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.Type: GrantFiled: December 14, 2016Date of Patent: March 9, 2021Assignee: Qualcomm IncorporatedInventors: David Francis Berdy, Changhan Hobie Yun, Shiqun Gu, Niranjan Sunil Mudakatte, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim
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Patent number: 10903240Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.Type: GrantFiled: May 3, 2019Date of Patent: January 26, 2021Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Daniel Daeik Kim, Matthew Michael Nowak, Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, David Francis Berdy
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Publication number: 20200388604Abstract: A multiple die (multi-die) module includes at least first and second dies of different technologies assembled so that edges of the first and second dies are in contact with each other. The edges of the first and second dies include protrusions and recesses configured to be press fitted. Edge interconnects are formed on the protrusions and/or the recesses such that when the first and second dies are assembled, they are electrically connected to each other.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Inventors: Byoungyong LEE, Changhan Hobie YUN
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Publication number: 20200266512Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.Type: ApplicationFiled: February 19, 2019Publication date: August 20, 2020Inventors: Kai LIU, Rui TANG, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
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Patent number: 10693432Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.Type: GrantFiled: May 17, 2018Date of Patent: June 23, 2020Assignee: QUALCOMMM IncorporatedInventors: Nosun Park, Changhan Hobie Yun, Jonghae Kim, Niranjan Sunil Mudakatte, Xiaoju Yu, Wei-Chuan Chen
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Patent number: 10614942Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.Type: GrantFiled: July 13, 2018Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, Mario Francisco Velez, Nosun Park, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Xiaoju Yu, Paragkumar Ajaybhai Thadesar, Jonghae Kim
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Patent number: 10607980Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.Type: GrantFiled: January 3, 2018Date of Patent: March 31, 2020Assignee: QUALCOMM IncorporatedInventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
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Publication number: 20200091094Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.Type: ApplicationFiled: September 14, 2018Publication date: March 19, 2020Inventors: Changhan Hobie YUN, Mario Francisco VELEZ, Nosun PARK, Niranjan Sunil MUDAKATTE, Wei-Chuan CHEN, Paragkumar Ajaybhai THADESAR, Christopher POLLOCK, Xiaoju YU, Rongguo ZHOU, Kai LIU, Jonghae KIM
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Patent number: 10582609Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.Type: GrantFiled: October 30, 2017Date of Patent: March 3, 2020Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, Jonghae Kim, Xiaoju Yu, Mario Francisco Velez, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Matthew Michael Nowak, Christian Hoffmann, Rodrigo Pacher Fernandes, Manuel Hofer, Peter Bainschab, Edgar Schmidhammer, Stefan Leopold Hatzl
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Patent number: 10553671Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.Type: GrantFiled: June 10, 2016Date of Patent: February 4, 2020Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez
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Publication number: 20200020473Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Inventors: Changhan Hobie YUN, Mario Francisco VELEZ, Nosun PARK, Wei-Chuan CHEN, Niranjan Sunil MUDAKATTE, Xiaoju YU, Paragkumar Ajaybhai THADESAR, Jonghae KIM
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Patent number: 10498307Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.Type: GrantFiled: September 14, 2017Date of Patent: December 3, 2019Assignee: QUALCOMM IncorporatedInventors: Mario Francisco Velez, Niranjan Sunil Mudakatte, Jonghae Kim, Changhan Hobie Yun, David Francis Berdy, Shiqun Gu, Chengjie Zuo
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Patent number: 10490348Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.Type: GrantFiled: June 24, 2016Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Mario Francisco Velez, Daeik Daniel Kim, Niranjan Sunil Mudakatte, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Yunfei Ma, Robert Paul Mikulka
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Patent number: 10490621Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.Type: GrantFiled: July 30, 2018Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Paragkumar Ajaybhai Thadesar, Mario Francisco Velez, Changhan Hobie Yun, Francesco Carrara, Jonghae Kim, Xiaoju Yu, Niranjan Sunil Mudakatte
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Publication number: 20190356294Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.Type: ApplicationFiled: May 17, 2018Publication date: November 21, 2019Inventors: Nosun PARK, Changhan Hobie YUN, Jonghae KIM, Niranjan Sunil MUDAKATTE, Xiaoju YU, Wei-Chuan CHEN
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Patent number: 10433425Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.Type: GrantFiled: August 1, 2018Date of Patent: October 1, 2019Assignee: QUALCOMM IncorporatedInventors: Kai Liu, Changhan Hobie Yun, Jonghae Kim, Mario Francisco Velez
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Publication number: 20190259780Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Inventors: Shiqun GU, Daniel Daeik KIM, Matthew Michael NOWAK, Jonghae KIM, Changhan Hobie YUN, Je-Hsiung Jeffrey LAN, David Francis BERDY