Patents by Inventor Changhan Hobie Yun

Changhan Hobie Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10103703
    Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka
  • Patent number: 10074625
    Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: September 11, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Mario Francisco Velez, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Daeik Daniel Kim, Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Robert Paul Mikulka
  • Patent number: 10069474
    Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: September 4, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Je-Hsiung Jeffrey Lan, David Francis Berdy, Yunfei Ma, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 10049815
    Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Jonghae Kim, Chengjie Zuo, Mario Francisco Velez, Changhan Hobie Yun
  • Patent number: 10038422
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Patent number: 10026546
    Abstract: An apparatus includes a substrate and a three-dimensional (3D) wirewound inductor integrated within the substrate. The apparatus further includes a capacitor coupled to the 3D wirewound inductor.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorported
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Jonghae Kim, David Francis Berdy
  • Publication number: 20180177052
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20180167054
    Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: David Francis BERDY, Changhan Hobie YUN, Shiqun GU, Niranjan Sunil MUDAKATTE, Mario Francisco VELEZ, Chengjie ZUO, Jonghae KIM
  • Publication number: 20180145062
    Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 24, 2018
    Inventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
  • Patent number: 9966426
    Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 8, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Niranjan Sunil Mudakatte, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Chengjie Zuo, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 9959964
    Abstract: A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: May 1, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, David Francis Berdy, Daeik Daniel Kim, Chengjie Zuo, Jonghae Kim, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Niranjan Sunil Mudakatte
  • Patent number: 9954267
    Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Daeik Daniel Kim, Mario Francisco Velez, Chengjie Zuo, David Francis Berdy, Jonghae Kim
  • Publication number: 20180090475
    Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Chengjie ZUO, Jonghae KIM, David Francis BERDY, Changhan Hobie YUN, Niranjan Sunil MUDAKATTE, Mario Francisco VELEZ, Shiqun GU
  • Patent number: 9930783
    Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20180083588
    Abstract: A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 22, 2018
    Inventors: Changhan Hobie YUN, Shiqun GU, Je-Hsiung Jeffrey LAN, Jonghae KIM, Niranjan Sunil MUDAKATTE, David Francis BERDY, Mario Francisco VELEZ, Chengjie ZUO
  • Publication number: 20180083589
    Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include a first insulator, a second insulator, a first subset of circuit elements disposed on a bottom surface of the first insulator, a second subset of circuit elements disposed on a top surface of the second insulator, one or more conductive couplings disposed between the first subset of circuit elements and the second subset of circuit elements.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Changhan Hobie YUN, Chengjie ZUO, David Francis BERDY, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Jonghae KIM
  • Publication number: 20180077803
    Abstract: Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 15, 2018
    Inventors: Changhan Hobie YUN, David Francis BERDY, Chengjie ZUO, Jonghae KIM, Niranjan Sunil MUDAKATTE, Mario Francisco VELEZ, Shiqun GU
  • Publication number: 20180062617
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Patent number: 9906318
    Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
  • Publication number: 20180054177
    Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.
    Type: Application
    Filed: August 18, 2016
    Publication date: February 22, 2018
    Inventors: Niranjan Sunil MUDAKATTE, David Francis BERDY, Changhan Hobie YUN, Chengjie ZUO, Shiqun GU, Mario Francisco VELEZ, Jonghae KIM