Patents by Inventor Changhan Hobie Yun

Changhan Hobie Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • OPEN-PASSIVATION BALL GRID ARRAY PADS
    Publication number: 20170221846
    Abstract: A conductive bump assembly may include a passive substrate. The conductive bump assembly may also include a conductive bump pad supported by the passive substrate and surrounded by a first passivation layer opening. The conductive bump assembly may further include a second passivation layer opening on the passive substrate. The second passivation layer opening may be merged with the first passivation layer opening surrounding the conductive bump pad proximate an edge of the passive substrate. The conductive bump assembly may also include a conductive bump on the conductive bump pad.
    Type: Application
    Filed: March 22, 2016
    Publication date: August 3, 2017
    Inventors: Daeik Daniel KIM, Mario Francisco VELEZ, Changhan Hobie YUN, Chengjie ZUO, David Francis BERDY, Jonghae KIM, Niranjan Sunil MUDAKATTE
  • Backside coupled symmetric varactor structure
    Patent number: 9721946
    Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, David Francis Berdy, Je-Hsiung Jeffrey Lan, Changhan Hobie Yun, Jonghae Kim
  • SKEWED CO-SPIRAL INDUCTOR STRUCTURE
    Publication number: 20170200550
    Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 13, 2017
    Inventors: Daeik Daniel KIM, David Francis BERDY, Chengjie ZUO, Changhan Hobie YUN, Jonghae KIM
  • MULTIPLEXER DESIGN USING A 2D PASSIVE ON GLASS FILTER INTEGRATED WITH A 3D THROUGH GLASS VIA FILTER
    Publication number: 20170187345
    Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.
    Type: Application
    Filed: March 10, 2016
    Publication date: June 29, 2017
    Inventors: Changhan Hobie YUN, Daeik Daniel KIM, Mario Francisco VELEZ, Chengjie ZUO, David Francis BERDY, Jonghae KIM
  • Three-dimensional wire bond inductor
    Patent number: 9692386
    Abstract: An inductor is provided on a substrate that includes a capacitor. The inductor comprises a series of wire loops. An end of the wire loop is wire bonded to the capacitor.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Mario Francisco Velez, Jonghae Kim, Daeik Daniel Kim, Changhan Hobie Yun
  • MIM CAPACITOR AND METHOD OF MAKING THE SAME
    Publication number: 20170178810
    Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: David Francis BERDY, Daeik Daniel KIM, Niranjan Sunil MUDAKATTE, Je-Hsiung Jeffrey LAN, Chengjie ZUO, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
  • Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits
    Patent number: 9673275
    Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: June 6, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Jonghae Kim, Matthew Michael Nowak
  • Superposed structure 3D orthogonal through substrate inductor
    Patent number: 9666362
    Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 30, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
  • Varactor device with backside contact
    Patent number: 9660110
    Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 23, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Jonghae Kim, Chengjie Zuo, Sang-June Park, Changhan Hobie Yun, Mario Francisco Velez, David Francis Berdy, Matthew Michael Nowak, Robert Paul Mikulka
  • ACOUSTIC RESONATOR DEVICES
    Publication number: 20170141756
    Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 18, 2017
    Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Je-Hsiung Jeffrey Lan, David Francis Berdy, Yunfei Ma, Robert Paul Mikulka, Jonghae Kim
  • THIN FILM MAGNET INDUCTOR STRUCTURE FOR HIGH QUALITY (Q)-FACTOR RADIO FREQUENCY (RF) APPLICATIONS
    Publication number: 20170140862
    Abstract: A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Inventors: Changhan Hobie YUN, David Francis BERDY, Daeik Daniel KIM, Chengjie ZUO, Jonghae KIM, Je-Hsiung Jeffrey LAN, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE
  • SOLENOID INDUCTOR
    Publication number: 20170133148
    Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.
    Type: Application
    Filed: November 7, 2016
    Publication date: May 11, 2017
    Inventors: Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Changhan Hobie YUN, Daeik Daniel KIM, David Francis BERDY, Jonghae KIM, Yunfei MA, Chengjie ZUO
  • METAL-INSULATOR-METAL (MIM) ARRAY FOR INTEGRATED RADIO FREQUENCY (RF) FILTER
    Publication number: 20170133996
    Abstract: A circuit includes a localized metal-insulator-metal (MIM) capacitor array in a radio frequency (RF) front end circuit, which is integrated on a first die, and includes a localized common shared ground node within the localized MIM capacitor array, a plurality of inductors, and a plurality of RF filters. Each of the plurality of RF filters includes a plurality of passive resonant frequency circuits, and each of the plurality of passive resonant frequency circuits is implemented utilizing one or more MIM capacitors in the localized MIM capacitor array, and one or more of the plurality of inductors. The plurality of inductors may be arranged at a periphery of the localized MIM capacitor array on the first die or integrated on a second die, which is coupled to the first die. Each of the MIM capacitors in the localized MIM capacitor array has a different capacitance value.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 11, 2017
    Inventors: Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • HIGH QUALITY FACTOR CAPACITORS AND METHODS FOR FABRICATING HIGH QUALITY FACTOR CAPACITORS
    Publication number: 20170125512
    Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.
    Type: Application
    Filed: December 11, 2016
    Publication date: May 4, 2017
    Inventors: Changhan Hobie YUN, Daeik Daniel KIM, Chengjie ZUO, Jonghae KIM, Mario Francisco VELEZ, Donald William KIDWELL JR, Jon Bradley LASITER, Kwan-Yu LAI, Jitae KIM, Ravindra Vaman SHENOY
  • ISOLATED COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) DEVICES FOR RADIO-FREQUENCY (RF) CIRCUITS
    Publication number: 20170117358
    Abstract: Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: Daeik Daniel Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Jonghae Kim, Matthew Michael Nowak
  • HIGH PERFORMANCE INDUCTORS
    Publication number: 20170110237
    Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.
    Type: Application
    Filed: June 23, 2016
    Publication date: April 20, 2017
    Inventors: Daeik Daniel KIM, Mario Francisco VELEZ, Changhan Hobie YUN, Niranjan Sunil MUDAKATTE, Jonghae KIM, Chengjie ZUO, David Francis BERDY
  • Radio-frequency (RF) shielding in fan-out wafer level package (FOWLP)
    Patent number: 9620463
    Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, David Francis Berdy, Mario Francisco Velez, Changhan Hobie Yun, Chengjie Zuo, Jonghae Kim, Matthew Michael Nowak
  • INTEGRATED CIRCUITS (ICS) ON A GLASS SUBSTRATE
    Publication number: 20170098663
    Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Shiqun Gu, Daeik Daniel Kim, Matthew Michael Nowak, Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, David Francis Berdy
  • WAFER LEVEL PACKAGE (WLP) BALL SUPPORT USING CAVITY STRUCTURE
    Publication number: 20170084565
    Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.
    Type: Application
    Filed: September 20, 2015
    Publication date: March 23, 2017
    Inventors: Mario Francisco VELEZ, David Francis BERDY, Changhan Hobie YUN, Jonghae KIM, Chengjie ZUO, Daeik Daniel KIM, Je-Hsiung Jeffrey LAN, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA
  • INTEGRATED CIRCUITS (ICS) ON A GLASS SUBSTRATE
    Publication number: 20170084531
    Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Shiqun Gu, Daeik Daniel Kim, Matthew Michael Nowak, Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, David Francis Berdy