Abstract: A motor control device for estimating a position of a rotor in a state in which a motor is stopped and a method for estimating a position of a rotor thereof are provided. The motor control device includes a power supply, a current sensor, and a processor. The processor determines whether a rotor position estimation execution condition is established, applies a phase voltage to a stator of the motor, if it is determined that the rotor position estimation execution condition is established, measures the current flowing in the stator, estimates a position of a rotor of the motor based on a first maximum current value among the measured current values, and determines whether to reattempt to estimate a position of the rotor based on a difference between the first maximum current value and a second maximum current value among the measured current values.

Abstract: Disclosed are a sensorless induction motor system including a controller configured to control operation of a motor by controlling a voltage applied to each phase of a stator, to set a stop waiting time expected to be required for the rotor to stop during stop control of the motor, to apply a pulse voltage to each phase of the stator a plurality of times after the stop waiting time, and to determine that the rotor is stopped when rotor position vectors having largest induced current deviations are observed as the same rotor position vector, and a control method thereof.

Abstract: The method for treating wastewater includes a first flocculation-and-sedimentation process and a second flocculation-and-sedimentation process, wherein the first flocculation-and-sedimentation process include: passing wastewater through a first flocculation reaction tank; passing the first treated water through a third flocculation reaction tank; passing the third treated water through a fourth flocculation reaction tank; and passing the fourth treated water through a first sedimentation tank to generate fifth treated water and sludge, and the second flocculation-and-sedimentation process include: passing the fifth treated water through a fifth flocculation reaction tank to generate sixth treated water; passing the sixth treated water through a sixth flocculation reaction tank to generate sixth treated water; passing the sixth treated water through a seventh flocculation reaction tank to generate eighth treated water; and passing the eighth treated water through a second sedimentation tank to generate ninth t

Abstract: A method for forming an oxide layer includes forming a protective interlayer oxide on sidewalls of a trench formed on a substrate, forming a silicon nitride layer on the protective interlayer oxide, by a plasma-enhanced atomic layer deposition (PE ALD) process utilizing nitrogen-containing process gas, the silicon nitride layer having a concentration gradient of nitrogen varying from high concentration away from the protective interlayer oxide to low concentration near the protective interlayer oxide, and performing a conversion process to oxidize the formed silicon nitride layer to at least partially convert the formed silicon nitride layer to a silicon oxide layer.

Abstract: Disclosed is a device for controlling travel. The device includes a sensor, a memory, and a controller. For example, the device may obtain, via a sensor (e.g., a LIDAR), a line recognition result associated with a road on which a vehicle is traveling, determine, based on the line recognition result, whether information, which comprises at least one of a curvature of the road or a curvature change rate of the road, satisfies a specified condition, and, based on the information satisfying the specified condition, generate calibrated line information using an expected curvature change rate, wherein the expected curvature change rate is determined based on: the curvature change rate, and at least one of an expected heading angle of the vehicle at a target point on the road, an expected curvature at the target point, or an expected lateral error at the target point.

Abstract: Proposed is a method of diagnosing abnormality of sensorless control of a motor for an air compressor, the method including estimating a speed of a motor in real time when a motor starts determining whether or not a preset condition for activating a function of diagnosing abnormality of sensorless control is satisfied, from a slope of the estimated speed of the motor performing control for decreasing an amount of electric current to be applied to the motor, in a case where the preset condition is satisfied computing an amount of decrease in the slope of the estimated speed of the motor while the amount of the electric current is decreased; and determining whether or not the sensorless control fails, by comparing the amount of the decrease in the slope of the speed of the motor with a preset value for confirming diagnosis of the abnormality of the sensorless control.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: Methods of manufacturing memory devices are provided. The method comprises forming a first epitaxial layer on a substrate; and forming a memory array on the first epitaxial layer, the memory array comprising a memory stack of alternating layers of an oxide material and a metal material on the first epitaxial layer, at least one memory cell extending from the first epitaxial layer through the memory stack, and a slit filled with a fill material adjacent to the at least one memory cell.

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

Abstract: A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate regions of the transistors and that decreases between adjacent transistors. The transistor stages may each be formed individually and incrementally, with the bottom source/drain region and the bit lines being completed first, followed by the gate region and the word lines, followed by the top source/drain regions and the capacitors.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.