Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

Abstract: Provided is a store device for digital therapeutic object including a processor, a storage unit configured to store a digital therapeutic object, and a memory electrically connected to the processor, at least one piece of code executed by the processor being stored in the memory, in which the memory stores the code causing the processor to process an XML-based DPR message requesting any one of registration, update of registration, abandonment of registration, usage, and abandonment of usage of the digital therapeutic object from a first external device.

Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and a plurality of internal electrodes, and external electrodes disposed on both ends of the capacitor body and connected to exposed portions of the plurality of internal electrodes, respectively. Each of the external electrodes includes a conductive layer disposed on the capacitor body to be connected to one or more of the plurality of internal electrodes, a conductive resin layer covering the conductive layer, and including a plurality of metal particles, a plurality of elastic fine powder particles each having an elastic powder particle and a metal film plated on a surface of the elastic powder particle, and a conductive resin surrounding the plurality of metal particles and the plurality of elastic fine powder particles and contacting the conductive layer, and a plating layer covering the conductive resin layer.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: A vehicle storage tank mounting device configured to mount an LPG storage tank at the rear position of a vehicle body frame using a storage tank mounting frame so as to absorb or block collision impact, thereby avoiding interference with the vehicle body frame and a propeller shaft. The vehicle storage tank mounting device is further configured to reliably absorb or block collision impact transmitted to the storage tank in the event of a side collision and a rear collision, and to satisfy collision safety performance and vehicle laws.

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

Abstract: The present invention relates to a compound for an organic optoelectronic device, represented by Chemical Formula 1; a composition for an organic optoelectronic device, including same; an organic optoelectronic device; and a display device. The description of Chemical Formula 1 is the same as that defined in the specification.

Abstract: A motor driving apparatus includes a motor an inverter driving the motor based on a switching signal, and a controller. The controller determines a current position estimated value of the motor by applying a zero-voltage vector pulse to the switching signal when entering the driving control of the motor, determines whether the motor is in a stop state according to an amount of change in the current position estimated value, and performs a pulse width modulation control by adjusting a duty ratio of the switching signal when the motor is determined to be in the stop state.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Abstract: A multilayer electronic component includes a body including a dielectric layer including Ba and Ti and an internal electrode alternately disposed with the dielectric layer, and including first and second surfaces opposing each other in a first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; a side margin portion disposed on the fifth and sixth surfaces; and external electrodes disposed on the third and fourth surfaces, wherein the side margin portion includes Sn and a transition metal, and wherein, in the side margin portion, a mole ratio of transition metal to Sn is 10 or more.

Abstract: A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate regions of the transistors and that decreases between adjacent transistors. The transistor stages may each be formed individually and incrementally, with the bottom source/drain region and the bit lines being completed first, followed by the gate region and the word lines, followed by the top source/drain regions and the capacitors.

Abstract: A sensorless induction motor system and a control method thereof includes a motor including a stator including windings forming a plurality of phases and a rotor including a permanent magnet, and a controller configured to control operation of the motor by controlling a voltage applied to each phase of the stator, to set a stop waiting time predicted to be necessary for the rotor to stop when the motor is controlled to stop, to apply a pulse voltage to each phase of the stator a plurality of times after the stop waiting time, and to conclude that the rotor has stopped when a minimum deviation value of an induced current is equal to or greater than a reference value.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.

Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.