Patents by Inventor Chao-Hung Lin

Chao-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204504
    Abstract: An electronic device including a signal processing circuit, an acceleration sensor, and an edge sensor is provided. The electronic device has a device body. The signal processing circuit operates in a sleep mode. The acceleration sensor senses an acceleration variation of the device body to generate an acceleration sensing signal. The acceleration sensor determines whether the acceleration sensing signal is continuously lower than an acceleration threshold for a preset length of time to wake up the signal processing circuit. When the acceleration sensor wakes up the signal processing circuit, the signal processor enables the edge sensor. The edge sensor senses a deformation variation of the device body to generate at least one deformation sensing signal. The signal processing circuit analyzes the deformation sensing signal to determine whether a drop event of the device body occurs. In addition, a drop warning method is also provided.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 12, 2019
    Assignee: HTC Corporation
    Inventors: Chao-Hung Lin, Chin-Yu Wang, Ming-Chang Chen
  • Publication number: 20180374757
    Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.
    Type: Application
    Filed: September 11, 2018
    Publication date: December 27, 2018
    Inventors: En-Chiuan Liou, Chao-Hung Lin, Yu-Cheng Tung
  • Patent number: 10147751
    Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the transparent shield. The method further includes removing portions of the transparent shield to form recessed regions in the transparent shield, where lateral bounds of the transparent shield extend beyond lateral bounds of the pixel array, and wherein the recessed regions are disposed in portions of the transparent shield that extend beyond the lateral bounds of the pixel array. The recessed regions are filled with a light blocking layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 4, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Publication number: 20180342426
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Publication number: 20180341109
    Abstract: Disclosed herein are systems, methods, and devices for implementing a heads-up display (HUD) that is viewable in conditions where a viewer is wearing a p-polarized eyewear, eyewear polarized between s-polarized and p-polarized, or not. Thus, employing the aspects disclosed herein, a viewer may realize all the benefits of a HUD implementation (for example, one implemented via a vehicle), while realizing all the benefits of wearing polarized eyewear.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 29, 2018
    Inventors: Chao-Hung Lin, Paul Fredrick Luther Weindorf, Sebastien Hervy, Jay P. Dark, Darrin W. Bruce, Ryo Kajiura, Claire Gerardin
  • Patent number: 10103062
    Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chao-Hung Lin, Yu-Cheng Tung
  • Publication number: 20180250858
    Abstract: Various examples provide a mold including a molding component and a supplementary component. The molding component may have a cavity, to enable a molten material to fill into the molding component to form an object. The supplementary component may include a bypass having a first opening located at a first position of the molding component and a second opening located at a second position of the molding component. The molten material may flow from the first position to the second position via the molding component, flow from the first opening to the second opening via the bypass and fill into the second position of the molding component through the second opening.
    Type: Application
    Filed: November 3, 2015
    Publication date: September 6, 2018
    Inventors: Chao-Hung LIN, Wei-Feng YEN, Guess WEI, Te-Shun LEE
  • Patent number: 10068808
    Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Publication number: 20180226447
    Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the transparent shield. The method further includes removing portions of the transparent shield to form recessed regions in the transparent shield, where lateral bounds of the transparent shield extend beyond lateral bounds of the pixel array, and wherein the recessed regions are disposed in portions of the transparent shield that extend beyond the lateral bounds of the pixel array. The recessed regions are filled with a light blocking layer.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 9, 2018
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Publication number: 20180226448
    Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a first transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the first transparent shield. A light blocking layer is deposited and disposed between lateral edges of the pixel array and lateral edges of the first transparent shield, and a second transparent shield is placed on the image sensor package, where the light blocking layer is disposed between the first transparent shield and the second transparent shield.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 9, 2018
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Publication number: 20180197981
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Publication number: 20180138088
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.
    Type: Application
    Filed: January 14, 2018
    Publication date: May 17, 2018
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9966404
    Abstract: An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material. A first transparent shield is adhered to the semiconductor material, and the pixel array is disposed between the semiconductor material and the first transparent shield. The image sensor package further includes a second transparent shield, where the first transparent shield is disposed between the pixel array and the second transparent shield. A light blocking layer is disposed between the first transparent shield and the second transparent shield, and the light blocking layer is disposed to prevent light from reflecting off edges of the first transparent shield into the pixel array.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 8, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Patent number: 9960123
    Abstract: The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. Next, an aligning mark is formed in the dicing region, wherein the aligning mark is a mirror symmetrical pattern and comprises a plurality of second patterns in the middle region and a plurality of third patterns in the third region, each third pattern has a plurality of lines and the lines comprises a plurality of inner lines which are formed by a sidewall image transfer (SIT) process.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9954108
    Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: April 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yi Chiu, Shih-Fang Hong, Chao-Hung Lin
  • Publication number: 20180108656
    Abstract: An asymmetrical fin structure includes a substrate. The substrate includes a top surface. A fin element extends from the substrate and connects to the substrate. The fin element includes two sidewalls respectively disposed at two opposite sides of the fin element. The sidewalls contact the top surface of the substrate. An epitaxial layer contacts and only covers one of the sidewalls. The other sidewall on the fin element does not contact any epitaxial layer.
    Type: Application
    Filed: November 10, 2016
    Publication date: April 19, 2018
    Inventors: Chao-Hung Lin, Tong-Jyun Huang, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9947792
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: April 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Patent number: 9916978
    Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 13, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chih-Kai Hsu, Yu-Hsiang Hung, Wei-Chi Cheng, Ssu-I Fu, Jyh-Shyang Jenq, Chao-Hung Lin
  • Patent number: 9905464
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9881831
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 30, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yi Chiu, Shih-Fang Hong, Chao-Hung Lin