Patents by Inventor Chao-Hung Lin

Chao-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9502252
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 9502410
    Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Hon-Huei Liu, Chao-Hung Lin, Nan-Yuan Huang, Jyh-Shyang Jenq
  • Publication number: 20160322366
    Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.
    Type: Application
    Filed: May 28, 2015
    Publication date: November 3, 2016
    Inventors: Chih-Kai Hsu, Chao-Hung Lin, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9484263
    Abstract: A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: November 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Li-Wei Feng, Shih-Hung Tsai, Jyh-Shyang Jenq, Ching-Ling Lin, Yi-Wen Chen, Chen-Ming Huang
  • Publication number: 20160315171
    Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.
    Type: Application
    Filed: June 1, 2015
    Publication date: October 27, 2016
    Inventors: Yu-Hsiang Hung, Chao-Hung Lin, Chih-Kai Hsu, Ssu-I Fu, Jyh-Shyang Jenq, Jun-Jie Wang, En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Ching-Wen Hung, Hung-Chan Lin, Yu-Hsiang Lin
  • Publication number: 20160300942
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.
    Type: Application
    Filed: May 5, 2015
    Publication date: October 13, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Chih-Kai Hsu, Yu-Hsiang Hung, Jyh-Shyang Jenq
  • Patent number: 9455194
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a material layer on the substrate; forming a plurality of first mandrels on the material layer of the first region and the second region; forming first spacers adjacent to the first mandrels; forming a hard mask on the first region; trimming the first spacers on the second region; removing the first mandrels; using the first spacers to remove part of the material layer for forming a plurality of second mandrels; forming second spacers adjacent to the second mandrels; removing the second mandrels; and using the second spacers to remove part of the substrate for forming a plurality of fin-shaped structures.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Chien-Ting Lin, Shih-Hung Tsai, Ssu-I Fu, Hon-Huei Liu, Shih-Fang Hong, Chao-Hung Lin, Jyh-Shyang Jenq
  • Publication number: 20160247678
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Application
    Filed: February 24, 2015
    Publication date: August 25, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng
  • Publication number: 20160233088
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.
    Type: Application
    Filed: March 4, 2015
    Publication date: August 11, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Publication number: 20160218179
    Abstract: A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core.
    Type: Application
    Filed: March 2, 2015
    Publication date: July 28, 2016
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Shih-Fang Hong, Chao-Hung Lin, Jyh-Shyang Jenq
  • Publication number: 20160203982
    Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.
    Type: Application
    Filed: March 3, 2015
    Publication date: July 14, 2016
    Inventors: Chao-Hung Lin, Shih-Fang Hong, Li-Wei Feng, Shih-Hung Tsai, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9384978
    Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Fang Hong, Li-Wei Feng, Shih-Hung Tsai, Ssu-I Fu, Jyh-Shyang Jenq
  • Publication number: 20160190287
    Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.
    Type: Application
    Filed: January 28, 2015
    Publication date: June 30, 2016
    Inventors: Chih-Kai Hsu, Chao-Hung Lin, Yu-Hsiang Hung, Ssu-I Fu, Ying-Tsung Chen, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9361782
    Abstract: An article anti-lost device comprises a plurality of sensors and a host. Each sensor comprises a recognition module and a sensor signal transceiver module. The host comprises a control module, a host signal transceiver module, a host warning module, an operation module and a display module. In an article anti-lost method, the host and the sensor are firstly paired, and then the sensor is combined with a to-be-monitored article and a warning distance is set. When a distance between the sensor and the host exceeds the warning distance, a warning signal is outputted, and an orientation and a distance of the sensor are prompted on the host. With the structure and the method, when the article leaves the user by a predetermined distance, the user can be reminded to prevent the article from getting lost or stolen.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: June 7, 2016
    Inventor: Chao-Hung Lin
  • Patent number: 9349833
    Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chao-Hung Lin, Ying-Tsung Chen, Chih-Kai Hsu, Ssu-I Fu, Jyh-Shyang Jenq, Shih-Hung Tsai
  • Patent number: 9349653
    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 24, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Ssu-I Fu, Chih-Sen Huang, Li-Wei Feng, Jyh-Shyang Jenq
  • Publication number: 20160104647
    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A substrate is provided. A fin structure and an inter-layer dielectric layer are formed on the substrate. A plurality of gate structures is formed on the substrate. A cap layer is formed on the gate structures. A hard mask is formed on the cap layer. A first patterned photoresist layer covering the gate structures is formed on the hard mask. The hard mask is etched and patterned to form a patterned hard mask, such that the patterned hard mask covers the gate structures. A second patterned photoresist layer including a plurality of openings corresponding to the fin structure is formed on the patterned hard mask. The cap layer and the inter-layer dielectric layer are etched to form a plurality of first trenches exposing part of the fin structure.
    Type: Application
    Filed: November 12, 2014
    Publication date: April 14, 2016
    Inventors: Chao-Hung Lin, Shih-Hung Tsai, Ssu-I Fu, Chih-Sen Huang, Li-Wei Feng, Jyh-Shyang Jenq
  • Patent number: 9307786
    Abstract: An automatic spring-roll shaping apparatus converts a spring-roll semiproduct into a spring-roll product, and includes a conveying belt disposed on a machine bed, and a rolling device. The rolling device includes a circular rotating tube rotatable between a shaping position, where the spring-roll semiproduct is rotated in a direction, and a release position, where the spring-roll semiproduct is released from the circular rotating tube so as to be moved by the conveying belt to pass past the circular rotating tube.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 12, 2016
    Inventor: Chao-Hung Lin
  • Publication number: 20160091699
    Abstract: A zoom lens includes a first lens group having negative refractive power, a second lens group having positive refractive power and a third lens group having positive refractive power. The second lens group is disposed between the first lens group and the third lens group. The second lens group includes at least an aspheric glass lens. Through using the aspheric glass lens, the imaging quality of the disclosed zoom lens is not sensitive to temperatures changes.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 31, 2016
    Inventor: CHAO-HUNG LIN
  • Patent number: 9291805
    Abstract: A zoom lens includes a first lens group having negative refractive power, a second lens group having positive refractive power and a third lens group having positive refractive power. The second lens group is disposed between the first lens group and the third lens group. The second lens group includes at least an aspheric glass lens. Through using the aspheric glass lens, the imaging quality of the disclosed zoom lens is not sensitive to temperatures changes.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 22, 2016
    Assignee: A-OPTRONICS TECHNOLOGY INC.
    Inventor: Chao-Hung Lin