Patents by Inventor Chao-I Wu

Chao-I Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375381
    Abstract: A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.
    Type: Application
    Filed: March 11, 2021
    Publication date: December 2, 2021
    Inventors: Chao-I WU, Shih-Lien Linus LU, Sai-Hooi YEONG
  • Publication number: 20210375928
    Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.
    Type: Application
    Filed: September 25, 2020
    Publication date: December 2, 2021
    Inventors: Chao-I Wu, Yu-Ming Lin, Han-Jong Chia
  • Publication number: 20210375344
    Abstract: A memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.
    Type: Application
    Filed: March 9, 2021
    Publication date: December 2, 2021
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
  • Publication number: 20210375937
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.
    Type: Application
    Filed: January 25, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-I Wu, Yu-Ming Lin, Sai-Hooi Yeong
  • Publication number: 20210249597
    Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chao-I Wu
  • Publication number: 20210242401
    Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.
    Type: Application
    Filed: July 1, 2020
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chao-I Wu
  • Publication number: 20180366644
    Abstract: A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.
    Type: Application
    Filed: June 15, 2017
    Publication date: December 20, 2018
    Inventors: Dai-Ying Lee, Chao-I Wu, Yu-Hsuan Lin
  • Patent number: 10158068
    Abstract: A ReRAM device is provided. The ReRAM device comprises a bottom electrode, a resistance switching layer disposed on the bottom electrode, a top electrode disposed on the resistance switching layer, a metal layer disposed on the top electrode, and a blocking layer covering the metal layer, wherein the blocking layer surrounds the metal layer and the top electrode.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 18, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Dai-Ying Lee, Chao-I Wu, Yu-Hsuan Lin
  • Publication number: 20180336946
    Abstract: A memory operating method and a memory operating device are provided. The memory operating method includes the following steps. A first stepping loop is performed. A second stepping loop is performed. In the first stepping loop, a first control voltage applied to a first control line is increased from a first initial value to a first final value which is larger than the first initial value, and a second control voltage applied to a second control line is fixed at a second initial value. In the second stepping loop, the first control voltage applied to the first control line is fixed at a fixing value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value which is larger than the second initial value.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 22, 2018
    Inventors: Yu-Hsuan Lin, Chao-I Wu, Dai-Ying Lee
  • Patent number: 9997567
    Abstract: A semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of silicon and silicon oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: June 12, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Dai-Ying Lee, Chao-I Wu, Yu-Hsuan Lin
  • Publication number: 20170206960
    Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
    Type: Application
    Filed: April 21, 2016
    Publication date: July 20, 2017
    Inventors: Chao-I Wu, Dai-Ying Lee, Ming-Hsiu Lee, Tien-Yen Wang
  • Patent number: 9711217
    Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 18, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-I Wu, Dai-Ying Lee, Ming-Hsiu Lee, Tien-Yen Wang
  • Patent number: 9627058
    Abstract: An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 18, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-I Wu, Tien-Yen Wang
  • Patent number: 9627054
    Abstract: A memory operating method comprises the following steps: a first read voltage is applied to the memory cell to read a first group of data levels of the memory cell; and if the data of the memory cell can not be read with the first read voltage, a second read voltage is applied to the memory cell to read a second group of data levels of the memory cell.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 18, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chao-I Wu
  • Patent number: 9620210
    Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: April 11, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Win-San Khwa, Chao-I Wu, Tzu-Hsiang Su, Hsiang-Pang Li
  • Patent number: 9583536
    Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: February 28, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Chao-I Wu, Yu-Hsuan Lin, Dai-Ying Lee
  • Patent number: 9564216
    Abstract: A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 7, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Win-San Khwa, Tzu-Hsiang Su, Chao-I Wu, Hsiang-Pang Li
  • Patent number: 9558823
    Abstract: A method is provided for operating a memory device including an array of memory cells including programmable resistive memory elements. Memory cells in the array are programmed to store data by applying program pulses to the memory cells to establish resistance levels within a number N of specified ranges of resistance, where each of the specified ranges corresponds to a particular data value. A drift recovery process is executed to the memory cells, including applying a recovery pulse having a pulse shape to a set of programmed memory cells, where memory cells in the set have resistance levels within two or more of the specified resistance ranges.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 31, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Win-San Khwa, Tzu-Hsiang Su, Chao-I Wu, Hsiang-Pan Li, Meng-Fan Chang
  • Publication number: 20170025473
    Abstract: A memory device having an array area and a periphery area is provided. The memory device includes a substrate, an isolation layer formed in the substrate, a first doped region formed on the isolation layer in the array area, a second doped region formed on the first doped region, a metal silicide layer formed on the second doped region, and a metal silicide oxide layer formed on the metal silicide layer.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Inventors: Erh-Kun Lai, Chao-I Wu, Yu-Hsuan Lin, Dai-Ying Lee
  • Publication number: 20160372195
    Abstract: An operating method, an operating system and a resistance random access memory (ReRAM) are provided. The operating method includes the following steps. A write voltage and a write current are set at a first predetermined voltage value and a first predetermined current value respectively. The write voltage and the write current are applied to a memory cell of the ReRAM for writing. Whether the write current reaches a second predetermined current value is verified, if a read current of the memory cell is not within a predetermined current range. The write current is increased, if the write current does not reach the second predetermined current value. Whether the write voltage reaches a second predetermined voltage value is verified, if the write current reaches the second predetermined current value. The write voltage is increased, if the write voltage does not reach the second predetermined voltage value.
    Type: Application
    Filed: August 28, 2015
    Publication date: December 22, 2016
    Inventors: Chao-I Wu, Tien-Yen Wang