Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract: A method for programming and erasing a PHINES memory device is comprising providing one or more additional pulses that are associated with a program or erase pulse, wherein the additional pulses are of similar polarity, but of lesser magnitude than the program or erase pulses. For an erase pulse on a PHINES memory device, two additional pulses can be utilized. For a program pulse on the source-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a source of the memory device. For a program pulse on the drain-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a drain of the memory device.

Abstract: A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the volatile programmable structure.

Abstract: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract: A semiconductor charge storage device includes a semiconductor substrate having a surface region. The semiconductor substrate is characterized by a first conductivity type. A charge trapping material overlies and is in contact with at least a portion of the surface region of the semiconductor substrate. The charge trapping material is characterized by a first dielectric constant and by a first charge trapping capability. The first dielectric constant is higher than a dielectric constant associated with silicon oxide. A dielectric material overlies and is in contact with at least a portion of the charge trapping material. The dielectric material is formed using a conversion of a portion of the charge trapping material for providing a second charge trapping capability. The device also includes a conductive material overlying the second dielectric. The conductive material is capable of receiving an electrical signal to cause electrical charges being trapped in the semiconductor charge storage device.

Abstract: Methods and structures are described for increasing a memory operation window in a charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing multiple bits per memory cell. In a first aspect of the invention, a first method to increase a memory operation window in a two-bit-per-cell memory is described by applying a positive gate voltage, +Vg, to erase a memory cell to a negative voltage level. Alternatively, a negative gate voltage, ?Vg, is applied to the two-bit-per-cell memory for erasing the memory cell to a negative voltage level. A second method to increase a memory operation window is to erase a memory cell to a voltage level that is lower than an initial voltage threshold level. These two erasing methods can be implemented either before a programming step (i.e., a pre-program erase operation) or after a programming step (i.e., a post-program erase operation).

Abstract: A method for improving the cycle endurance of a memory device during a memory cell programming operation includes applying a first negative bias pulse measured from a gate to a drain of the memory device at a level sufficient to induce hot hole injection into a nitride region of the gate adjacent to the drain, and applying a second negative bias pulse measured from the gate to the drain on the memory device, wherein the magnitude of the second negative bias pulse is less than the magnitude of the first negative bias pulse, and the duration of the second negative bias pulse is less than the duration of the first negative bias pulse.

Abstract: A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.

Abstract: The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. The programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

Abstract: A method for erasing a plurality of two-bit memory cells, each two-bit memory cell comprises a first bit and a second bit. A reference voltage is applied to a first bit line and a second bit line, the first bit line being associated with the first bits of each two-bit memory cell and the second bit line associated with the second bits of each two-bit memory cell. Then a control activation voltage is applied to a first bit line select and a second bit line select, each bit line associated with the first bits and the second bits of each memory cell, respectively. Then an operating voltage is applied to a plurality of word lines associated with each two-bit memory cell, wherein the operating voltage is between 14 and 20 volts.

Abstract: An operating method of a memory array is provided. The operating method includes performing a programming operation.

Abstract: A method of operating a multi-level cell is provided. The method includes the following the steps. (a) The multi-level cell is operated until a threshold voltage is larger than a pre-programming threshold voltage. And (b) the multi-level cell is operated until the threshold voltage is larger than a target programming threshold voltage and smaller than the pre-programming threshold voltage. Moreover, between the step (a) and the step (b), further comprises (c) A first verification step is performed. If the threshold voltage is smaller than the pre-programming threshold voltage, then repeat the step (a). Furthermore, after the step (b), further comprises (d) a second verification step is performed. If the threshold voltage is larger than the pre-programming threshold voltage, repeat the step (b), and if the threshold voltage is smaller than the target programming threshold voltage, repeat the steps (a)-(d).

Abstract: The present invention provides a method for applying a double-side-bias operation to a virtual ground array memory composed of a matrix of N-bit memory cells. In a first embodiment, the virtual ground array is programmed by a double-side-bias method which applies the same or similar biasing voltage simultaneously on the source region and drain region of a selected charge trapping memory cell so that the left bit and the right bit of the selected charge trapping memory cell are programmed together. In a second embodiment, the virtual ground array is erased by a double-side-bias method which applies the same or similar biasing voltage simultaneously on source regions and regions of a plurality of charge trapping memory cells in the virtual ground array so that the left bit and the right bit of each charge trapping memory cell are erased together.

Abstract: Methods are described for double-side-bias of multi-level-cell memory devices comprising a NAND array that comprises a plurality of charge trapping memory cells. A memory device is programmed by a double-side-bias electron injection technique and is erased by a double-side-bias hole injection technique. Each charge trapping memory cell includes 2n logic states, such as four binary logic states of a logic 00 state, a logic 01 state, a logic 10 state and a logic 11 state. The memory device can be programmed by a double-side-bias multi-level-cell program method either with a variable DSB (Vd/Vs) voltage or with a variable gate bias voltage Vg.

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.

Abstract: A charge trapping memory having a plurality of memory cells in which each memory cell is capable of storing in a left charge storage site and a right charge storage site, multiple bits per memory cell. A memory operation window the memory cell is improved by biasing the memory cell for programming the right charge storage site improved when the left charge storage site stores charge sufficient to establish a negative threshold voltage, or a threshold voltage lower than an initial voltage level.

Abstract: A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.