Abstract: The present invention discloses a division method and system for distributed renewable-energy electricity generation clusters, where the method includes: obtaining electric power consumption-absorption data of the electricity-generation clusters; extracting and analyzing the absorbed electricity quantities of the corresponding target single electricity generators or the consumed electricity quantities of the corresponding target energy consumption nodes; constructing and determining consumption-absorption matching groups for a plurality of electricity generator sets and energy consumption districts according to distances from the target single electricity generators to the target energy consumption nodes, and executing division for the electricity-generation clusters. According to the present invention, energy waste can be avoided, and then management efficiency is increased.

Abstract: A method for manufacturing semiconductor structure includes: forming a gate structure on a substrate; forming a source portion and a drain portion in the substrate respectively at two opposite sides of the gate structure; forming a protection layer over the substrate, the gate structure, the source portion and the drain portion; forming an opening in the protective layer to expose the gate structure; and performing a silicidation process to form a silicide layer on the exposed gate structure.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.

Abstract: The present disclosure is related to a file processing method, electronic apparatus and storage medium, the file processing method including: updating a file list according to file access information for a file in a storage device, wherein the file list contains file inode numbers of files to be defragmented; defragmenting the files to be defragmented corresponding to the file inode numbers in the storage device, according to the updated file list, in response to the occurrence of a triggering event.

Abstract: The present application discloses a MEMS device comprising a proof mass, an anchor, a main suspension, and a flexible stopper. The main suspension respectively connects to the proof mass and the anchor at both ends thereof. An end of the flexible stopper is connected to the anchor, and another end of the flexible stopper extends toward the proof mass. Thereby, the present application reduces the impact of adding the flexible stopper on the proof mass, maintaining the sensing sensitivity of the MEMS device.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: A memory cell includes a bottom electrode, a top electrode, and a variable resistance layer. The top electrode is disposed over the bottom electrode. The variable resistance layer is sandwiched between the bottom electrode and the top electrode. A first portion of a bottom surface of the variable resistance layer and a second portion of the bottom surface of the variable resistance layer are parallel to each other and are located at different level heights.

Abstract: A memory device includes a memory cell, a protection coating, and a first sidewall spacer. The memory cell is disposed over an inter-metal dielectric (IMD) layer. The memory cell includes a bottom electrode, a top electrode and a resistance-switchable structure between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the resistance-switchable structure. The protection coating consists of a binary compound of carbon and hydrogen. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.

Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.

Abstract: The present disclosure relates to a heat radiator and a turbo fracturing unit comprising the same. The heat radiator includes: a cabin; a heat radiation core disposed at the inlet and configured to allow a gas/air to pass therethrough; a gas/air guide device disposed at the outlet and configured to suction the air within the cabin to the outlet; and noise reduction structure disposed within the cabin, which is of a structure progressively converging to the outlet. The heat radiator is configured to enable the gas/air to enter the cabin via the inlet, then sequentially pass through the heat radiation core, a surface of the noise reduction structure and the gas/air guide device, and finally be discharged out of the cabin. The heat radiator according to the present disclosure is a suction-type heat radiator which can regulate the speed of the gas/air guide device based on the temperature of the gas/air at the inlet, thereby avoiding energy waste and unnecessary noise.

Abstract: This application provides an interface calling simulation method for developing an application program performed by an electronic device. The electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The electronic device identifies, within a simulated interface set for a simulation interface corresponding to the target interface. The simulated interface set includes simulated interfaces that simulate real interfaces in the application program. The electronic device compares the interface calling information of the target interface with interface configuration information of the simulated interface.

Abstract: A receiver includes at least one receive channel. The at least one receive channel includes a first receive channel, and the first receive channel includes a first inductor and a first receiving circuit that are coupled to each other. The first inductor is configured to filter a received signal of a first frequency band to obtain a first received signal. A self-resonant frequency of the first inductor is in an interference frequency band corresponding to the first frequency band. The first receiving circuit is configured to process the first received signal.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first active region and a second active region adjacent to the first active region, a first gate stack extending across the first active region in a first direction, an isolation feature extending across the second active region in the first direction; and a first gate-cut feature sandwiched between the first gate stack and the isolation feature.

Abstract: Disclosed are a magnetic core structure and a magnetic component. The magnetic core structure includes N winding columns and two cover plates, and N is a positive integer, wherein each winding column is provided with a first hollow channel, the two cover plates are disposed at two ends of each winding column, each cover plate is provided with N first through holes, the N winding columns are in a one-to-one correspondence with the N first through holes of each cover plate, and the first hollow channel of each winding column is communicated with the first through holes located on two sides thereof and corresponding thereto. Therefore, the channels for air flow can be added, so that the heat dissipation efficiency is improved when the magnetic core structure is applied to the magnetic component.

Abstract: A panel assembly includes a panel frame having one or more air outlets surrounding a reference axis. The one or more air outlets include an adjustable port having a port inner edge close to the reference axis and a port outer edge away from the reference axis. On the reference axis, a projection of the port inner edge is located on a side of a projection of the port outer edge facing an outer end of the reference axis. The panel assembly further includes an adjustable plate movably arranged at the adjustable port and having a low-wind-feeling position, at which a plate inner edge of the adjustable plate is close or linked to the port inner edge, and a radial air outlet configured to output air in a direction away from the reference axis is formed between the port outer edge and a plate outer edge of the adjustable plate.

Abstract: In various examples, a technique for securely transmitting CAN (Controller Area Network) messages is disclosed that includes receiving, using a cryptographic engine, a message from an application to be transmitted over a CAN (Controller Area Network) bus, wherein the cryptographic engine executes a secure firmware and is implemented on an on-die discrete processor. The technique further includes accessing, using the secure firmware, a key from a plurality of keys associated with an authentication process from a secure memory associated with the cryptographic engine. Additionally, the technique includes computing an authentication tag using the key and the message and transmitting the message with the authentication tag over the CAN bus to a destination address.

Abstract: The present disclosure is related to a file processing method, electronic apparatus and storage medium, the file processing method including: updating a file list according to file access information for a file in a storage device, wherein the file list contains file inode numbers of files to be defragmented; defragmenting the files to be defragmented corresponding to the file inode numbers in the storage device, according to the updated file list, in response to the occurrence of a triggering event.

Abstract: A semiconductor structure includes a semiconductor-on-insulator (SOI) substrate including a handle substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure that vertically extends through the top semiconductor layer and the buried insulating layer, and includes a first inner insulating liner laterally surrounding a first portion of the top semiconductor layer that is located in a first device region in a plan view, a first non-insulating moat structure laterally surrounding the first inner insulating liner, and a first outer insulating liner that laterally surrounds the first non-insulating moat structure; and a resistive memory array located on the first portion of the top semiconductor layer, and located entirely within the first device region in the plan view.