Abstract: An off-road vehicle has a cooling system with a cooling module positioned above the prime mover assembly. An air-guide guides ambient air to the cooling module. Air chamber intake ports of the air-guide are positioned rearwardly and positioned further from the longitudinal mid-plane than the vehicle doors, such that doors guide air into and through the air chamber intake ports for airflow through the cooling module. The cooling module includes an intercooler, a radiator and a fan assembly, positioned against each other in that order so air is fanned through both the intercooler and radiator. The prime mover assembly is supported at least in part by a support cradle. A power package/cradle length ratio of the power package length to the support cradle length is in the range from 1.3 to 1.9.

Abstract: A raised floor and an assembling method thereof includes a plurality of raised floor boards, wherein a plurality of raised floor boards are assembled and connected to form an integrated floor, an edge of the integrated floor close to the wall is supported by a leveling beam, and leveling screws are arranged below connecting positions of two adjacent raised floor boards, a reserved expansion joint is arranged between the edge of the integrated floor and the wall, and a position above the integrated floor close to the wall is fixedly connected with frame beam by an expansion screw. An edge of the raised floor board body structure is processed, so that the raised floor boards can be assembled through lap joint and connection of structures, and supported through the leveling screws when they are in mutually lap joint for assembly.

Abstract: The present invention discloses a division method and system for distributed renewable-energy electricity generation clusters, where the method includes: obtaining electric power consumption-absorption data of the electricity-generation clusters; extracting and analyzing the absorbed electricity quantities of the corresponding target single electricity generators or the consumed electricity quantities of the corresponding target energy consumption nodes; constructing and determining consumption-absorption matching groups for a plurality of electricity generator sets and energy consumption districts according to distances from the target single electricity generators to the target energy consumption nodes, and executing division for the electricity-generation clusters. According to the present invention, energy waste can be avoided, and then management efficiency is increased.

Abstract: A semiconductor device includes: a substrate; common electrode structures stacked on the substrate in a first direction; stacked array structures including first electrode structures, where the first electrode structures are stacked on the substrate in the first direction and are electrically connected to the common electrode structures disposed at the same layers with the first electrode structures; first lead-out structures stacked in the first direction and connected to the common electrode structures disposed at the same layers with the first lead-out structures, where the first lead-out structures include first lead-out wires and first pseudowires that are disposed opposite to each other, and the first lead-out wires and the first pseudowires in the different first lead-out structures are alternately disposed in the first direction.

Abstract: The present invention discloses a method and a system for controlling an overvoltage in a photovoltaic court based on a floating neutral voltage, including: acquiring, by a controller, a voltage U of the photovoltaic court and a voltage U0 of a transformer neutral point; comparing acquired voltage data with a set threshold; generating control instructions of offsetting and compensation according to a comparison result; and receiving the instructions by a neutral voltage regulator, and controlling a voltage. The present invention introduces a floating neutral line between a photovoltaic power supply and a grid-connected transformer neutral point, and arranges a neutral voltage regulator on the floating neutral line. By adjusting its direction and size, the neutral voltage regulator can adapt to the voltage problem of the court in different states. Meanwhile, by adjusting the voltage on the grid-connected transformer neutral point side, the voltage of the grid-connected transformer neutral point is zero.

Abstract: A data storage includes: determining, in response to receiving an IO request, a data response level for the IO request; determining, according to the data response level, a storage area for storing data to be written corresponding to the IO request in a UFS device, the UFS device comprises a high speed buffer and a normal storage area; and writing the data to be written into the determined storage area, wherein the high speed buffer comprises a first area, a second area, and a third area, and the UFS device is configured block data stored in the third area is from being flushed into the normal storage area. The speeds of the high speed buffer are greater than the speeds of the normal storage area. The first area, the second area, and the third area and the normal storage area correspond to different data response levels, respectively.

Abstract: A three-dimensional semiconductor memory, includes a substrate, a plurality of active layers arranged in an array on the substrate, a plurality of bit lines, a plurality of storage nodes, and a shielding structure. Each of the bit lines is connected to one end of each of the active layers. The bit lines extend in a second direction, and are stacked on the substrate in a third direction. Each of the storage nodes is connected to the other end of each of the active layers. The shielding structure includes a body portion and a plurality of shielding portions. The shielding portions extend in the second direction. The body portion and the shielding portions each are formed of a conductive material, and the body portion is electrically connected to the shielding portions. At least one shielding portion is disposed between adjacent bit lines in the third direction.

Abstract: There is provided methods and devices for reducing write amplification of a storage apparatus, including monitoring a running status of at least one application; acquiring historical write data of a first application from an application history record to estimate a storage space for current foreground running of the first application based on monitoring the running status of the first application among the at least one application switching to foreground running; determining a storage apparatus adjustment command based on the estimated storage space for the current foreground running of the first application, the storage apparatus including a high-speed storage portion and a low-speed storage portion, the storage apparatus adjustment command including adjustments to a storage space of a variable area in the high-speed storage portion, and the storage apparatus configured to store data generated in response to the at least one application running in the variable area.

Abstract: A communication device includes: one or more voltage conversion circuits. The one or more voltage conversion circuits are separately coupled to a power supply of the communication device. A voltage sampling circuit is coupled to the power supply, and/or the voltage sampling circuit is coupled to an output end of at least one of the one or more voltage conversion circuits. A controller is configured to: control the voltage sampling circuit to collect voltages output by the power supply or voltages output by a first voltage conversion circuit in a plurality of sending timeslots or a plurality of receiving timeslots of the communication device; and determine a real voltage of the power supply based on the voltages output by the power supply or the voltages output by the first voltage conversion circuit in the plurality of sending timeslots or the plurality of receiving timeslots of the communication device.

Abstract: The present disclosure provides a memory and a manufacturing method therefor, and an electronic device. The memory includes multiple bit line functional groups, multiple storage units, and a staircase structure, and each of the bit line functional groups includes a first bit line structure, multiple second bit line structures, and multiple selection transistors. The first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. Multiple second bit line structures are provided on a first side of the first bit line in a third direction, a staircase structure is provided on a second side of the first bit line in the third direction, and multiple conductive stairs of the staircase structure are respectively coupled to corresponding first bit lines.

Abstract: A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.

Abstract: A memory and an electronic device are provided. The memory includes bit line functional groups spaced apart along a first direction, memory cells, a first staircase structure, and a second staircase structure located on a base substrate; each bit line functional group includes a first bit line, and a second bit line and a third bit line respectively coupled to the first bit line, the first bit line extending along a second direction, the second and third bit lines extending along a third direction; the second bit line and the memory cells are located on one side of the first bit line in the third direction, the third bit line and the first and second staircase structures are located on the other side of the first bit line in the third direction, and the first and second staircase structures are located on opposite sides of the third bit line.

Abstract: A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.

Abstract: The present invention discloses a division method and system for distributed renewable-energy electricity generation clusters, where the method includes: obtaining electric power consumption-absorption data of the electricity-generation clusters; extracting and analyzing the absorbed electricity quantities of the corresponding target single electricity generators or the consumed electricity quantities of the corresponding target energy consumption nodes; constructing and determining consumption-absorption matching groups for a plurality of electricity generator sets and energy consumption districts according to distances from the target single electricity generators to the target energy consumption nodes, and executing division for the electricity-generation clusters. According to the present invention, energy waste can be avoided, and then management efficiency is increased.

Abstract: The present disclosure is related to a file processing method, electronic apparatus and storage medium, the file processing method including: updating a file list according to file access information for a file in a storage device, wherein the file list contains file inode numbers of files to be defragmented; defragmenting the files to be defragmented corresponding to the file inode numbers in the storage device, according to the updated file list, in response to the occurrence of a triggering event.

Abstract: The present disclosure relates to a heat radiator and a turbo fracturing unit comprising the same. The heat radiator includes: a cabin; a heat radiation core disposed at the inlet and configured to allow a gas/air to pass therethrough; a gas/air guide device disposed at the outlet and configured to suction the air within the cabin to the outlet; and noise reduction structure disposed within the cabin, which is of a structure progressively converging to the outlet. The heat radiator is configured to enable the gas/air to enter the cabin via the inlet, then sequentially pass through the heat radiation core, a surface of the noise reduction structure and the gas/air guide device, and finally be discharged out of the cabin. The heat radiator according to the present disclosure is a suction-type heat radiator which can regulate the speed of the gas/air guide device based on the temperature of the gas/air at the inlet, thereby avoiding energy waste and unnecessary noise.

Abstract: This application provides an interface calling simulation method for developing an application program performed by an electronic device. The electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The electronic device identifies, within a simulated interface set for a simulation interface corresponding to the target interface. The simulated interface set includes simulated interfaces that simulate real interfaces in the application program. The electronic device compares the interface calling information of the target interface with interface configuration information of the simulated interface.