Abstract: A heterojunction bipolar transistor structure is provided, including a substrate and a multi-layer structure formed on the substrate. The multi-layer structure includes a current clamping layer, and the current clamping layer can be disposed in a collector layer, disposed in a sub-collector layer, or interposed between a collector layer and a sub-collector layer. An electron affinity of the current clamping layer is less than an electron affinity of an epitaxial layer formed on the current clamping layer.

Abstract: A setting method of in-memory computing simulator includes: performing a plurality of test combinations by an in-memory computing device and recording a plurality of first estimation indices corresponding to the plurality of test combinations respectively, wherein each of the plurality of test combinations includes one of a plurality of neural network models and one of a plurality of datasets, executing a simulator according to the plurality of test combinations by a processing device and recording a plurality of second estimation indices corresponding to the plurality of test combinations respectively, wherein the simulator has a plurality of adjustable settings; calculating a correlation sum according to the plurality of first estimation indices and the plurality of second estimation indices by the processing device, and performing an optimal algorithm to search an optimal parameter in the setting space constructed by the plurality of settings so that the correlation sum is maximal.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.

Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.

Abstract: A matte film for hot pressing and a manufacturing method thereof are provided. The manufacturing method includes steps of forming at least one polyester composition into an unstretched polyester thick film and stretching the unstretched polyester thick film in a machine direction (MD) and a transverse direction (TD). The polyester composition includes 81% to 97.9497% by weight of a polyester resin, 0.02% to 2% by weight of an antioxidative ingredient, 0.0003% to 1% by weight of a nucleating agent, 0.01% to 2% by weight of a flow aid, 0.01% to 2% by weight of a polyester modifier, 0.01% to 2% by weight of an inorganic filler, and 2% to 10% by weight of silica particles. The polyester resin has an intrinsic viscosity between 0.60 dl/g and 0.80 dl/g.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: A memory device and a semiconductor die are provided. The memory device includes single-level-cells (SLCs) and multi-level-cells (MLCs). Each of the SLCs and the MLCs includes: a phase change layer; and a first electrode, in contact with the phase change layer, and configured to provide joule heat to the phase change layer during a programming operation. The first electrode in each of the MLCs is greater in footprint area as compared to the first electrode in each of the SLCs.

Abstract: A raised floor and an assembling method thereof includes a plurality of raised floor boards, wherein a plurality of raised floor boards are assembled and connected to form an integrated floor, an edge of the integrated floor close to the wall is supported by a leveling beam, and leveling screws are arranged below connecting positions of two adjacent raised floor boards, a reserved expansion joint is arranged between the edge of the integrated floor and the wall, and a position above the integrated floor close to the wall is fixedly connected with frame beam by an expansion screw. An edge of the raised floor board body structure is processed, so that the raised floor boards can be assembled through lap joint and connection of structures, and supported through the leveling screws when they are in mutually lap joint for assembly.

Abstract: A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.

Abstract: A method for forming a semiconductor structure is provided. The method includes: providing a base, the base including a first area and second areas located outside the first area, the first area including stack structures and isolation trenches alternately arranged in a first direction, the first direction being any direction in a plane where the base is located; performing ion implantation on sidewalls of the stack structure in the first direction, so as to form an active virtual connecting layer extending in the first direction and partially located in the isolation trenches; and forming a gate structure on a surface of the active virtual connecting layer.

Abstract: A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

Abstract: A device for reducing noise in a radio signal received in the FM band is proposed, including: a module for demodulating the radio signal, adapted to generate a demodulated radio signal on the basis of the received radio signal; a noise suppression module adapted to replace a temporal sequence of the demodulated radio signal with a denoised sequence; a module for controlling the noise suppression module, adapted to control the activation of the noise suppression module. The noise reduction device further including a module for analyzing the frequency spectrum of the received radio signal. The control module is configured to control the noise suppression module according to an activation strategy chosen from among several predetermined activation strategies depending on the spectral content of the received radio signal.

Abstract: Methods, systems, and apparatuses for erosion rate monitoring for wafer fabrication equipment are described to support determining a real-time edge ring erosion rate for an edge ring used in manufacturing memory devices or other semiconductor devices. A manufacturing system may support a real-time edge ring erosion rate determination using force sensors, which may measure the weight of the edge ring. The controller may correlate the measured weight to a height of the edge ring. The controller may use the height to adjust a vertical placement of the edge ring, or one or more other manufacturing variables, during manufacturing operations, which may compensate for edge ring erosion and reduce or eliminate yield loss when manufacturing a memory device or other semiconductor device.

Abstract: This application provides an interface calling simulation method for developing an application program performed by an electronic device. The electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The electronic device identifies, within a simulated interface set for a simulation interface corresponding to the target interface. The simulated interface set includes simulated interfaces that simulate real interfaces in the application program. The electronic device compares the interface calling information of the target interface with interface configuration information of the simulated interface.