Abstract: A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

Abstract: A data displaying system and a data displaying method are provided. The data displaying system includes a storage device and a processor. The processor executes a plurality of modules in the storage device. A collection module accesses a database to retrieve historical display data. The historical display data include a plurality of fields. An analysis module calculates a plurality of length values of the historical display data in the respective fields to generate length data. The analysis module counts a distribution of the length data and generates target field widths corresponding to the fields based on a threshold and the distribution of the length data. An interface module outputs the target field widths to an electronic device, which allows the electronic device to display current display data in the electronic device based on the target field widths and thus improve user experience.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.

Abstract: A memory cell includes a dielectric structure, a storage element structure, and a top electrode. The storage element structure is disposed in the dielectric structure, and the storage element structure includes a first portion and a second portion. The first portion includes a first side and a second side opposite to the first side, where a width of the first side is less than a width of the second side. The second portion is connected to the second side of the first portion, where a width of the second portion is greater than the width of the first side. The top electrode is disposed on the storage element structure, where the second portion is disposed between the first portion and the top electrode.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Abstract: A transformer including a core structure is provided. The core structure includes a first plate and a second plate opposite to the first plate, two opposite side posts and a plurality of winding posts. At least one of the first plate and the second plate has a first cross-section with a cross-sectional area of Ap. The two side posts are disposed between the first plate and the second plate. At least one of the two side posts has a second cross-section with a cross-sectional area of Ao. The winding posts are disposed between the first plate and the second plate and between the two side posts. At least one of the winding posts has a third cross-section with a cross-sectional area of Ac. 1.5Ac>Ap>0.5Ac, and 0.1Ac<Ao<0.5Ac.

Abstract: An expansion apparatus with a power management function includes a power supply device, an expansion module and a control module. The power supply device includes a controller and an output terminal, and provides a predetermined power through the output terminal. The expansion module includes an input port coupled to the output terminal, and multiple output ports operable to be coupled to multiple electronic apparatuses. The control module has a full-power output mode and a disabled mode, and receives a device identifier provided by the controller through the input port to learn the predetermined power, so as to selectively adjust the output ports to operate in the full-power output mode or the disabled mode based on the predetermined power, thereby limiting a total power consumed by the electronic apparatuses and the expansion module to be less than or equal to the predetermined power.

Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

Abstract: Provided is an interconnect structure including: a first conductive feature, disposed in a first dielectric layer; a second conductive feature, disposed over the first conductive feature and the first dielectric layer; a via, disposed between the first and second conductive features and being in direct contact with the first and second conductive features; and a barrier structure, lining a sidewall and a portion of a bottom surface of the second conductive feature, a sidewall of the via, a portion of a top surface of the first conductive feature, and a top surface of the first dielectric layer.

Abstract: A semiconductor device includes a memory cell having a bottom electrode, a memory element, a selector, a top electrode and a connecting structure. The memory element is disposed on the bottom electrode. The selector is disposed on the memory element. The top electrode is disposed on the selector. The connecting structure is electrically connecting the memory element to the selector, wherein the connecting structure includes a base portion and a pillar portion. The base portion disposed on the memory element. The pillar portion is disposed on the base portion, wherein the pillar portion is physically connected to the selector, and includes a tapered pillar foot.

Abstract: Disclosed is a method for solving parameters of extension/compression springs by an AC salp swarm algorithm, including the following steps. Determine design parameters to be solved of an extension/compression spring. Construct an objective function for solving the design parameters of the extension/compression spring based on a design objective of the extension/compression spring, wherein the design objective of the extension/compression spring is to minimize the weight of the extension/compression spring. Determine constraints of the design parameters of the extension/compression spring. Perform iterative optimization on the design parameters of the extension/compression spring using an AC salp swarm algorithm to obtain a globally optimal solution, and output the globally optimal solution as solved design parameters of the extension/compression spring, wherein the AC salp swarm algorithm is obtained by adding an AC operation between individuals during an iteration process of an existing salp swarm algorithm.

Abstract: Herein disclosed are an electronic component testing system and a time certification method. The electronic component testing system comprising a testing device and an interface device. The testing device comprises a backboard, and the backboard electrically connected to at least one test board and comprising a time certification component. The interface device, electrically connected to the testing device, provides a test instruction. Wherein the time certification component stores an authorization start time and an authorization end time. Wherein the testing device starts a test procedure according to the test instruction, the time certification component updates the authorization start time to a first stop time of the test procedure after the test procedure is completed.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.