Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

Abstract: Disclosed is a transformer, including a first resonance coil, a primary coil, a secondary coil, a second resonance coil, and a magnetic core which includes a first base, a second base, a third base, a magnetic cover, a first center pillar, a second center pillar, a third center pillar, a fourth center pillar, a fifth center pillar, and a sixth center pillar. The first and second center pillars extend from the first base towards the second base. The third and fourth center pillars extend from the second base towards the third base. The fifth and sixth center pillars extend from the third base towards the magnetic cover. The first resonance coil surrounds the first and second center pillars. The primary coil surrounds the third and fourth center pillars. The secondary coil surrounds the third and fourth center pillars. The second resonance coil surrounds the fifth and sixth center pillars.

Abstract: Disclosed is an inductor, including a magnetic core, a first inner coil and a first outer coil. The magnetic core includes a first base, a magnetic cover, a first center pillar and a first side wall. The first center pillar and the first side wall extend from the first base towards the magnetic cover. The first inner coil surrounds the first center pillar. The first outer coil surrounds the first center pillar. The first inner coil is wound between the first outer coil and the first center pillar. In the inductor, both the first inner coil and the first outer coil are wound around the first center pillar, thereby reducing the overall height of the magnetic core, which is convenient for users to design and use.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.

Abstract: Embodiments of the present disclosure relate to a multi-node storage system and a data deduplication method thereof. The method includes determining a similarity hash value of a super block, wherein the similarity hash value indicates similarity between super blocks The method further includes comparing the similarity hash value of the super block with a feature similarity hash value of a node of the multi-node storage system to determine whether the super block matches the node and, in response to determining that the super block matches the node, allocating the super block to the node.

Abstract: In an embodiment, a device includes: a first metallization layer over a substrate, the substrate including active devices; a first bit line over the first metallization layer, the first bit line connected to first interconnects of the first metallization layer, the first bit line extending in a first direction, the first direction parallel to gates of the active devices; a first phase-change random access memory (PCRAM) cell over the first bit line; a word line over the first PCRAM cell, the word line extending in a second direction, the second direction perpendicular to the gates of the active devices; and a second metallization layer over the word line, the word line connected to second interconnects of the second metallization layer.

Abstract: A magnetic device includes a base plate, a cover plate, a first winding column, a second winding column, a primary winding, a secondary winding and a supporting column. The base plate, having a first concave portion, is opposite to the cover plate. The first winding column and the second winding column are disposed between the bottom plate and the cover plate, respectively. The primary winding and the secondary winding are wound around the first winding column and the second winding column. The supporting column is disposed between the base plate and the cover plate. A first concave portion concaves from a first side of the base plate towards the first winding column and the second winding column along multiple directions. The primary winding and the secondary winding are wound and stacking along an extension direction of the first winding column and the second winding column.

Abstract: A middleware system and a service request result returning method are provided. The middleware system communicates with a service request end and a plurality of servers. A processor receives a plurality of service requests sent by the service request end, and writes the service requests into a service request queue. The service agent unit outputs the service requests to the servers according to the service request queue. The servers respond with a plurality of service request results to the service agent unit. The time agent unit detects the time when the processor receives the service requests, so as to write a plurality of service request end messages and a plurality of service request times of the service requests into a service request time queue. The message distributor builds a message distribution table, and outputs the service request results to the service request end according to the message distribution table.

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

Abstract: A method for detecting and attenuating the impact of interference in a signal of a radio receiver with multiple tuners. The method includes providing a first input signal RF1 to a first tuner T1; simultaneously providing a second input signal RF2 to a second tuner T2; simultaneously producing a first intermediate high injection signal IFH1, by the first tuner T1, using the first input signal RF1 filtered on a first frequency fE, and a first intermediate low injection signal IFB2, by the second tuner T2, using the second input signal RF2 filtered on the first frequency fE; comparing the first intermediate high injection signal IFH1 and the first intermediate low injection signal IFB2; selecting one out of the first intermediate high injection signal IFH1 and the first intermediate low injection signal IFB2 to be decoded by the radio receiver.

Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.

Abstract: A transformer includes a bobbin and a plurality of coils wound on the bobbin. The plurality of coils includes a first primary coil; a second primary coil, located above the first primary coil and electrically connected to the first primary coil; a secondary coil, located between the first primary coil and the second primary; a first auxiliary coil, located above the second primary coil; and a second auxiliary coil, located on the first auxiliary coil and electrically connected to the first auxiliary coil.

Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Abstract: Embodiments of the present disclosure relate to a multi-node storage system and a data deduplication method thereof. The method includes determining a similarity hash value of a super block, wherein the similarity hash value indicates similarity between super blocks The method further includes comparing the similarity hash value of the super block with a feature similarity hash value of a node of the multi-node storage system to determine whether the super block matches the node and, in response to determining that the super block matches the node, allocating the super block to the node.

Abstract: A method, an electronic device, and a computer program product for storage management are provided. The method includes: acquiring a lock attribute record in a lock attribute record chain from a data protection network for backing up data, data protection servers of the data protection network reaching a consensus on the lock attribute record chain, the lock attribute record including a first attribute value of an attribute of a lock operation, the lock operation being used for preventing a backup of the data stored in a storage server from being tampered with; acquiring, based on the lock attribute record, a second attribute value of the attribute of the lock operation from the storage server; and generating, based on determining that the first attribute value does not match the second attribute value, an alarm indicating that the backup is tampered with. This solution can better prevent data from being tampered with.

Abstract: A semiconductor structure includes a first channel layer and a first barrier layer on the first channel layer. The first channel layer has a first potential well adjacent to the interface between the first channel layer and the first barrier layer. The semiconductor structure further includes a second channel layer on the first barrier layer, a second barrier layer on the second channel layer, and an intermediate layer between the second channel layer and the second barrier layer. The second channel layer has a second potential well adjacent to the interface between the second channel layer and the intermediate layer. The intermediate layer has a greater energy gap than either the first barrier layer or the second barrier layer. The energy gap of the first barrier layer is no less than the energy gap of the second barrier layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.