Abstract: A semiconductor device includes a first electrode, a first dielectric layer, a second electrode and an insulating layer. The first dielectric layer is disposed on the first electrode. The second electrode is disposed in the first dielectric layer. The insulating layer is disposed in the first dielectric layer and between the second electrode and the first electrode and between the second electrode and the first dielectric layer. The first electrode and the second electrode are electrically isolated by the insulating layer.

Abstract: The present disclosure relates to an antibody against Aquaporin-4 (AQP4). These peptide-specific AQP4 antibodies play a role to create a NMO model and contribute for investigating the NMO disease mechanisms and developing the strategy of the treatment.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.

Abstract: A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.

Abstract: A fan-out package structure of an image sensing device includes an image sensing unit having an image sensor with opposite sensing surface and connecting surface, a spacer layer surrounding a central portion of the sensing surface, and a light-transmitting cover plate disposed on the spacer layer spaced apart from and covering the sensing surface. An image signal processor is disposed on the connecting surface. A redistribution layer covers the image signal processor and the connecting surface, and includes a fan-out area. An encapsulation layer is disposed on the fan-out area, surrounds and covers an outer periphery of the image sensing unit, and allows a top surface of the light-transmitting cover plate to be exposed. A method of manufacturing a fan-out package structure of an image sensing device is also disclosed.

Abstract: Water conservancy construction sewage treatment mechanism, including a support mounting cylinder, where a variable-diameter sedimentation cylinder is arranged at one end of the support mounting cylinder, one half of the cylinder wall of the support mounting cylinder is a thin wall and the other half is a thick wall, and the thin wall and the thick wall are disposed oppositely. The water conservancy construction sewage treatment mechanism also includes: a variable-diameter diversion cylinder, which is arranged on the thin wall at the other end of the support mounting cylinder; several displacement diversion modules, which are arranged on the thick wall of the support mounting cylinder and include guide displacement structures and combined diversion structures; and a magnetic attraction displacement adjusting structure, which is arranged on the outer side of the thick wall of the support mounting cylinder and is matched with the guide displacement structures and the combined diversion structures.

Abstract: Provided is a memory cell including a selector disposed over a substrate, a memory element and a connecting pad. The selector includes a bottom electrode, an ovonic threshold switch layer on the bottom electrode, an inter-electrode over the ovonic threshold switch layer, and an intermediate layer between the ovonic threshold switch layer and the inter-electrode. The memory element is disposed on the selector. The connecting pad is disposed on the memory element.

Abstract: A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.

Abstract: An ultrasonic device is provided and includes an action member, a driving member and a rotating shaft connected to the driving member. The action member provides ultrasonic vibration and vibrates the driving member, so that the driving member oscillates to make the rotating shaft and a cutter oscillate in the same direction together, so the cutter can remove scrap by oscillating during the cutting operation.

Abstract: The present disclosure relates to a heat radiator and a turbo fracturing unit comprising the same. The heat radiator includes: a cabin; a heat radiation core disposed at the inlet and configured to allow a gas/air to pass therethrough; a gas/air guide device disposed at the outlet and configured to suction the air within the cabin to the outlet; and noise reduction structure disposed within the cabin, which is of a structure progressively converging to the outlet. The heat radiator is configured to enable the gas/air to enter the cabin via the inlet, then sequentially pass through the heat radiation core, a surface of the noise reduction structure and the gas/air guide device, and finally be discharged out of the cabin. The heat radiator according to the present disclosure is a suction-type heat radiator which can regulate the speed of the gas/air guide device based on the temperature of the gas/air at the inlet, thereby avoiding energy waste and unnecessary noise.

Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.

Abstract: A memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.

Abstract: Manufacture of a ferroelectric random-access memory device includes forming a first electrode and an intermetal dielectric (IMD) layer over the first electrode. The IMD layer has a first surface on a first side of the IMD layer distal from the first electrode and a second surface on a second side of the IMD layer proximate to the first electrode. A via is created through the IMD layer, which is aligned with the first electrode underneath and has a side wall extending from the first surface of the IMD layer to the second surface of the IMD layer. A ferroelectric layer is deposited over the IMD layer. The ferroelectric layer includes a first part within the via and a second part extending laterally out from the via over the first surface of the IMD layer, the second part thereafter being removed by chemical mechanical polishing.

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Abstract: An electronic device receives an interface calling request for a target interface in an application program. The interface calling request includes interface calling information of the target interface. The device performs an interface query in a simulated interface set that simulates real interfaces in the application program. In accordance with a determination, based on the interface query, that a target simulation interface corresponding to the target interface exists in the simulated interface set, the device intercepts the interface calling request. The device compares the intercepted interface calling information with interface configuration information of the target simulated interface. In accordance with a determination that the interface calling information matches the interface configuration information, the device obtains simulated response data corresponding to the target simulation interface. The device outputs calling response data of the interface calling request.

Abstract: A method for preparing urea ammonium nitrate solution from waste nitric acid after stripping tin from circuit board includes: causing the waste nitric acid after stripping tin and the ammonia water to undergo neutralizing and precipitating reaction through acid-base neutralization, filtering, thereby obtaining tin-containing filter mud and a primary filtrate; adding iron powders into to the primary filtrate to initiate copper-iron replacement reaction, filtering, thereby obtaining iron-containing coarse copper powders and a secondary filtrate; adding hydrogen peroxide to the secondary filtrate, filtering, thereby obtaining an iron-containing sludge and a tertiary filtrate; adding a heavy metal capturing agent to the tertiary filtrate, filtering, thereby obtaining a heavy metal sludge and an ammonium nitrate solution; measuring a concentration of the ammonium nitrate solution, adding urea and liquid fertilizer corrosion inhibitor to obtain a urea/ammonium nitrate dilute solution, evaporating and concentrating

Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.

Abstract: Memory stacks and method of forming the same are provided. A memory stack includes a bottom electrode layer, a top electrode layer and a phase change layer between the bottom electrode layer and the top electrode layer. A width of the top electrode layer is greater than a width of the phase change layer. A first portion of the top electrode layer uncovered by the phase change layer is rougher than a second portion of the top electrode layer covered by the phase change layer.