Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250146590
    Abstract: An integrated air valve structure includes a main body and two air valves. The main body is formed with two air passages not communicated with each other, a plurality of through holes disposed corresponding to the two air passages, and two valve mounting seats. One valve mounting seat is disposed corresponding to one of the through holes, the other valve mounting seat is disposed corresponding to two of the through holes belonging to the two air passages. The two air valves are disposed on the two valve mounting seats, each air valves includes an air plug facing at least one of the through holes, a valve body assembled with one of the two valve mounting seats for the air plug to move therein, and a coil disposed on the valve body for generating magnetic force to change a position of the air plug.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 8, 2025
    Inventors: Tsun-Hsiang WEN, Chia-Yu YU, Peng ZHAO, Yung-Cheng LIU, Chao-Wen HUANG
  • Patent number: 12293929
    Abstract: A transfer system adaptable to performing levelling alignment includes a transfer head that picks up micro devices, the transfer head having a plurality of pick-up heads protruded from a bottom surface of the transfer head; and a levelling fixture configured to perform levelling alignment for the transfer head, the levelling fixture having a plurality of cavities that are concave downwards to correspondingly accommodate the pick-up heads respectively.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: May 6, 2025
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chun-Jen Weng, Chao-Wen Wu
  • Patent number: 12294308
    Abstract: The present disclosure relates to a circuit and a method for compensating output of voltage source, and the voltage source. The circuit for compensating an output of a voltage source, comprises: a sensing unit, a first adjustment unit, an amplifier unit, and a second adjustment unit. The first adjustment unit is coupled in parallel with the sensing unit, and configured to generate at least one pole point and/or at least one zero point in a transfer function of the circuit; the second adjustment unit is configured to generate at least one zero point in the transfer function of the circuit. Therefore, the first adjustment unit, and the second adjustment unit are arranged for generating adjustable zero points and pole points in the transfer function of the voltage source, so as to obtain a higher loop bandwidth.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 6, 2025
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Chao Wen, Tai Ma
  • Publication number: 20250140743
    Abstract: A structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. The first semiconductor die includes integrated circuit regions. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. The gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-An Kuo, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
  • Patent number: 12288752
    Abstract: A semiconductor package includes a first die and a through via. The through via is electrically connected to the first die. The through via includes a first conductive layer having a first width, a second conductive layer having a second width different from the first width and a first seed layer disposed aside an interface between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12284699
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: April 22, 2025
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • Publication number: 20250125632
    Abstract: A communication control unit for establishing a communication line between an electrical unit and a battery unit, wherein there is an electrical power transmission line between the electrical unit and the battery unit, the communication control unit being configured to: in response to determining that a communication interference occurs between the communication control unit and the electrical unit and/or the battery unit during a period when the electrical unit supplies electrical power to the battery unit or acquires electrical power from the battery unit, switch a first communication protocol currently used for communication between the communication control unit and the electrical unit and/or the battery unit to a second communication protocol, wherein the second communication protocol has a higher anti-interference capability than the first communication protocol.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 17, 2025
    Inventors: Ye ZHANG, Chao WEN, Hai Bo MA
  • Publication number: 20250125294
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventor: Chao Wen Wang
  • Patent number: 12274885
    Abstract: Methods and devices for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. A method performed by the EI includes scanning one or more channels for an advertisement notice transmitted by the IMD in accordance with a scanning schedule, wherein the scanning schedule defines a temporal pattern of scanning windows that are separated by one or more scanning intervals. The method also includes changing the scanning schedule, in response to a duration of the scanning the one or more channels exceeding a predetermined threshold without a valid advertisement notice being received by the EI from the IMD, and scanning the one or more channels for the advertisement notice in accordance with the scanning schedule as changed, wherein the scanning schedule as changed defines a different temporal pattern of scanning windows that are separated by one or more scanning intervals.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: April 15, 2025
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Samir Shah, Heidi Hellman, Reza Shahandeh, Tejpal Singh, Youjing Huang, Chao-Wen Young
  • Publication number: 20250118707
    Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die, a first gap-fill layer along sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer, and a first die connector in the first bonding layer. The first die connector may be directly over an interface between the first die and the first gap-fill layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Po-Cheng Chen, Chao-Wen Shih, Min-Chien Hsiao, Kuo-Chiang Ting, Yen-Ming Chen
  • Patent number: 12272674
    Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.
    Type: Grant
    Filed: July 23, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12273935
    Abstract: A method, system and external instrument are provided. The method initiates a communication link between an external instrument (EI) and an implantable medical device (IMD), established a first connection interval for conveying data packets between the EI and IMD and monitors a connection criteria that includes at least one of a data throughput requirement. A battery indicator or link condition of the communications link is between the IMD and EI. The method further changes from the first connection interval to a second connection interval based on the connection criteria.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: April 8, 2025
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Xing Pei, Reza Shahandeh
  • Patent number: 12266847
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: December 24, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 12266619
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • Patent number: 12261159
    Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 25, 2025
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Hsing-Ying Lee, Chun-Bin Wen
  • Publication number: 20250062259
    Abstract: A semiconductor device and methods of manufacture are discussed herein. A device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Inventors: Min-Chien Hsiao, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
  • Patent number: 12224265
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20250046738
    Abstract: Provided is packages and method of fabricating the same. The package includes a first die, a second die, and an inductor. The second die is bonded to the first die through a bonding structure thereof. The inductor is located in the bonding structure. The inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Tzuan-Horng Liu, Jen-Li Hu
  • Publication number: 20250031963
    Abstract: Computer implemented methods and systems are provided that comprise, under control of one or more processors of a medical device, where the one or more processors are configured with specific executable instructions. The methods and systems include sensing circuitry configured to define a sensing channel to collect biological signals, memory configured to store program instructions, a processor configured to implement the program instructions to at least one of analyze the biological signals, manage storage of the biological signals or deliver a therapy, and communication circuitry configured to wirelessly communicate with at least one other implantable or external device, the communication circuitry configured to transition between a sleep state, a partial awake state and a fully awake state.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Reza Shahandeh, Gabriel A. Mouchawar
  • Publication number: 20250040254
    Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih