Abstract: A bicycle trainer includes a base having a base portion and a standing portion, a supporting frame rotationally pivoted on the standing portion of the base around an axle, a cassette module mounted on the supporting frame and having multiple sprockets, and a flywheel module mounted on the supporting frame. A height adjusting member includes the standing portion, the supporting frame and a fixing element. The fixing element is placed in or between the standing portion and the supporting frame for keeping the supporting frame at a predetermined angle with respect to the standing portion.

Abstract: A semiconductor device includes a semiconductor structure including a conductive feature therein, a bitline over the semiconductor structure, a spacer on a sidewall of the bitline, wherein the first spacer is made of SiCO, a dielectric layer over a top surface of the bitline; and a contact in contact with the dielectric layer and the spacer and connected to the conductive feature of the semiconductor structure.

Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded within the substrate. The dielectric layer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded within the substrate. The dielectric layer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded within the substrate. The dielectric layer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded within the substrate. The dielectric layer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

Abstract: A manufacturing method of a memory device includes forming bit line structures over a substrate, forming a conductive structure between and over the bit line structures, in which the conductive structure exposes a portion of the bit line structures, forming a spacer including an air gap along sidewalls of the bit line structures, and forming an isolation structure between the conductive structure and one of the bit line structures, in which the isolation structure includes a first insulation material layer sealing the air gap and a second insulation material layer over the first insulation material layer, and the first insulation material layer and the second insulation material layer are in contact with the one of the bit line structures.

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

Abstract: A first wafer having a two-dimensional array of first semiconductor dies including arrays of first top metal bonding pads attached to a top surface of a first carrier wafer. A second wafer having a two-dimensional array of second semiconductor dies including arrays of second top metal bonding pads and arrays of second bottom metal bonding pads bonded to the first wafer by performing a first metal-to-metal bonding process in which the arrays of first top metal bonding pads are bonded to the arrays of second bottom metal bonding pads through first intermetallic diffusion. A third wafer having a two-dimensional array of third semiconductor dies including arrays of third bottom metal bonding pads bonded to the second wafer by performing a second metal-to-metal bonding process in which the arrays of second top metal bonding pads are bonded to the arrays of third bottom metal bonding pads through second intermetallic diffusion.

Abstract: A first wafer having a first portion closer to a first surface and a thicker second portion connected with the first portion and closer to the second surface opposite to the first surface is provided. A second wafer is provided to bond with the first wafer. An edge trimming process is performed to form a trench penetrating through the second wafer and extending beyond the first portion and extending into the second portion. After bonding dies to the second wafer, a filling material is formed over the dies and the first and second wafers, wrapping around and between the dies, covering the first and second wafers, and partially filling the trench. A wafer thinning process is performed to remove the second portion and partially remove the filling material in the trench to level the surface of the thinned first wafer with the surface of the thinned filling material.

Abstract: An integrated air valve structure includes a main body and two air valves. The main body is formed with two air passages not communicated with each other, a plurality of through holes disposed corresponding to the two air passages, and two valve mounting seats. One valve mounting seat is disposed corresponding to one of the through holes, the other valve mounting seat is disposed corresponding to two of the through holes belonging to the two air passages. The two air valves are disposed on the two valve mounting seats, each air valves includes an air plug facing at least one of the through holes, a valve body assembled with one of the two valve mounting seats for the air plug to move therein, and a coil disposed on the valve body for generating magnetic force to change a position of the air plug.

Abstract: A transfer system adaptable to performing levelling alignment includes a transfer head that picks up micro devices, the transfer head having a plurality of pick-up heads protruded from a bottom surface of the transfer head; and a levelling fixture configured to perform levelling alignment for the transfer head, the levelling fixture having a plurality of cavities that are concave downwards to correspondingly accommodate the pick-up heads respectively.

Abstract: The present disclosure relates to a circuit and a method for compensating output of voltage source, and the voltage source. The circuit for compensating an output of a voltage source, comprises: a sensing unit, a first adjustment unit, an amplifier unit, and a second adjustment unit. The first adjustment unit is coupled in parallel with the sensing unit, and configured to generate at least one pole point and/or at least one zero point in a transfer function of the circuit; the second adjustment unit is configured to generate at least one zero point in the transfer function of the circuit. Therefore, the first adjustment unit, and the second adjustment unit are arranged for generating adjustable zero points and pole points in the transfer function of the voltage source, so as to obtain a higher loop bandwidth.

Abstract: A structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. The first semiconductor die includes integrated circuit regions. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. The gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.

Abstract: A semiconductor package includes a first die and a through via. The through via is electrically connected to the first die. The through via includes a first conductive layer having a first width, a second conductive layer having a second width different from the first width and a first seed layer disposed aside an interface between the first conductive layer and the second conductive layer.

Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.

Abstract: A communication control unit for establishing a communication line between an electrical unit and a battery unit, wherein there is an electrical power transmission line between the electrical unit and the battery unit, the communication control unit being configured to: in response to determining that a communication interference occurs between the communication control unit and the electrical unit and/or the battery unit during a period when the electrical unit supplies electrical power to the battery unit or acquires electrical power from the battery unit, switch a first communication protocol currently used for communication between the communication control unit and the electrical unit and/or the battery unit to a second communication protocol, wherein the second communication protocol has a higher anti-interference capability than the first communication protocol.

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Abstract: Methods and devices for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. A method performed by the EI includes scanning one or more channels for an advertisement notice transmitted by the IMD in accordance with a scanning schedule, wherein the scanning schedule defines a temporal pattern of scanning windows that are separated by one or more scanning intervals. The method also includes changing the scanning schedule, in response to a duration of the scanning the one or more channels exceeding a predetermined threshold without a valid advertisement notice being received by the EI from the IMD, and scanning the one or more channels for the advertisement notice in accordance with the scanning schedule as changed, wherein the scanning schedule as changed defines a different temporal pattern of scanning windows that are separated by one or more scanning intervals.