Abstract: The embodiments of the application discloses a method and apparatus for pose estimation, and an electronic device. A specific implementation of the method includes: obtaining an observation information sequence corresponding to a human target part, wherein the human target part comprises at least one of the following: a head and a hand; determining an initial human joint point feature based on the observation information sequence; and performing feature interaction based on the initial human joint point feature, and estimating a human pose using an interaction feature, so as to obtain human pose information. This implementation makes the estimated human pose more accurate and realistic.

Abstract: A stacking structure including a first die and a second die bonded with the first die is provided. The first die has a first region and a second region encircled by the first region. The first die includes first metallization structures having a first seal ring structure and a first bonding structure having first dummy pads located over the first seal ring structure. The second die includes second metallization structures having a second seal ring structure and a second bonding structure having second dummy pads located over the second seal ring structure. The first die and the second die are bonded through bonding of the first and second bonding structures. The first and second seal ring structures are substantially vertically aligned, and the first dummy pads are respectively bonded with the second dummy pads.

Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Abstract: In some examples, a system detects disabling of a driver of a storage control feature included in a main processor of the system, where the storage control feature to manage access of a storage device. In response to detecting the disabling of the driver of the storage control feature included in the main processor, the system initiates a remediation action to prevent a fault in the system.

Abstract: Embodiments include methods of forming three-dimensional packages and the packages resulting therefrom. The packages may utilize a bridge die to electrically connect one die to another die and at least one additional die adjacent to the bridge die. The height-to-width ratio of the gap between the bridge die and the at least one additional die is controlled by thinning the bridge die to be thinner than the at least one additional die. The packages may utilize landing structures to adjoin a dielectric material of an attached die to a metallic landing structure of a base die.

Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

Abstract: Provided is packages and method of fabricating the same. The package includes a first die, a second die, and an inductor. The second die is bonded to the first die through a bonding structure thereof. The inductor is located in the bonding structure. The inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.

Abstract: In example implementations, an apparatus is provided. The apparatus includes an expansion slot, a peripheral device connected to the expansion slot, and a processor communicatively coupled to the expansion slot. The processor is to determine that a compatibility of the peripheral device with active state power management (ASPM) is unknown, provide a notification to indicate that the compatibility of the peripheral device with ASPM is unknown, wherein the notification provides a selection between disabling ASPM for the peripheral device or enabling ASPM for the peripheral device, and configure a basic input/output system (BIOS) setting in accordance with the selection to control the ASPM for the peripheral device.

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Abstract: Computer implemented methods and systems are provided that comprise, under control of one or more processors of a medical device, where the one or more processors are configured with specific executable instructions. The methods and systems include sensing circuitry configured to define a sensing channel to collect biological signals, memory configured to store program instructions, a processor configured to implement the program instructions to at least one of analyze the biological signals, manage storage of the biological signals or deliver a therapy, and communication circuitry configured to wirelessly communicate with at least one other implantable or external device, the communication circuitry configured to transition between a sleep state, a partial awake state and a fully awake state.

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

Abstract: A method includes bonding a first package component on a composite carrier, and performing a first polishing process on the composite carrier to remove a base carrier of the composite carrier. The first polishing process stops on a first layer of the composite carrier. A second polishing process is performed to remove the first layer of the composite carrier. The second polishing process stops on a second layer of the composite carrier. A third polishing process is performed to remove a plurality of layers in the composite carrier. The plurality of layers include the second layer, and the third polishing process stops on a dielectric layer in the first package component.

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

Abstract: This disclosure is directed to a ball valve having an outer valve body, a valve core, a rotational assembly, and a functional assembly. The valve core is accommodated in the outer valve body, and the valve core has a flow channel defined therein. The rotational assembly is connected to the valve core for turning the valve core. A portion of the functional assembly is disposed in the flow channel.

Abstract: A package includes a first package structure and a second package structure stacked on and electrically connected to the first package structure. The first package structure includes an integrated circuit, conductive structures, and an encapsulant. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate. Sidewalls of the semiconductor substrate of the first chip are aligned with sidewalls of the semiconductor substrate of the fourth chip. The encapsulant laterally encapsulates the integrated circuit and the conductive structures. A topmost surface of the encapsulant is coplanar with top surfaces of the conductive structures. A bottommost surface of the encapsulant is coplanar with bottom surfaces of the conductive structures.

Abstract: The embodiments of the disclosure provide a method, apparatus, and electronic device for hand three-dimensional reconstruction. One specific implementation of the method includes: obtaining hand images acquired at at least two angles of view; determining an initial hand three-dimensional reconstruction result corresponding to each of the hand images based on a predetermined hand three-dimensional reconstruction network, wherein the hand three-dimensional reconstruction result comprises a hand three-dimensional model and a hand key point; and fusing the initial hand three-dimensional reconstruction results corresponding to the hand images acquired at the at least two angles of view to obtain a fused hand three-dimensional reconstruction result. With consistency of a plurality of angles of views, the implementation may make the fused hand three-dimensional reconstruction result more accurate.

Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.

Abstract: A method includes: forming first semiconductor dies in a first wafer, each die of the first semiconductor dies comprising: first active devices over a front-side of a first semiconductor substrate; performing first probe tests on the first wafer; based on the first probe tests, classifying each die of the first semiconductor dies as a first good die, a first marginal die, or a first bad die; forming second semiconductor dies in a second wafer; performing second probe tests on the second wafer; based on the second probe tests, classifying each die of the second semiconductor dies as a second good die, a second marginal die, or a second bad die; and bonding the second wafer to the first wafer, each die of the first semiconductor dies aligning with a corresponding die of the second semiconductor dies.