Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118707
    Abstract: An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die, a first gap-fill layer along sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer, and a first die connector in the first bonding layer. The first die connector may be directly over an interface between the first die and the first gap-fill layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Po-Cheng Chen, Chao-Wen Shih, Min-Chien Hsiao, Kuo-Chiang Ting, Yen-Ming Chen
  • Patent number: 12272674
    Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.
    Type: Grant
    Filed: July 23, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12273935
    Abstract: A method, system and external instrument are provided. The method initiates a communication link between an external instrument (EI) and an implantable medical device (IMD), established a first connection interval for conveying data packets between the EI and IMD and monitors a connection criteria that includes at least one of a data throughput requirement. A battery indicator or link condition of the communications link is between the IMD and EI. The method further changes from the first connection interval to a second connection interval based on the connection criteria.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: April 8, 2025
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Xing Pei, Reza Shahandeh
  • Patent number: 12266847
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: December 24, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 12266619
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • Patent number: 12261159
    Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 25, 2025
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Hsing-Ying Lee, Chun-Bin Wen
  • Publication number: 20250062259
    Abstract: A semiconductor device and methods of manufacture are discussed herein. A device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 20, 2025
    Inventors: Min-Chien Hsiao, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
  • Patent number: 12224265
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20250046738
    Abstract: Provided is packages and method of fabricating the same. The package includes a first die, a second die, and an inductor. The second die is bonded to the first die through a bonding structure thereof. The inductor is located in the bonding structure. The inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Tzuan-Horng Liu, Jen-Li Hu
  • Publication number: 20250031963
    Abstract: Computer implemented methods and systems are provided that comprise, under control of one or more processors of a medical device, where the one or more processors are configured with specific executable instructions. The methods and systems include sensing circuitry configured to define a sensing channel to collect biological signals, memory configured to store program instructions, a processor configured to implement the program instructions to at least one of analyze the biological signals, manage storage of the biological signals or deliver a therapy, and communication circuitry configured to wirelessly communicate with at least one other implantable or external device, the communication circuitry configured to transition between a sleep state, a partial awake state and a fully awake state.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Reza Shahandeh, Gabriel A. Mouchawar
  • Publication number: 20250040254
    Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20250028385
    Abstract: The embodiments of the application discloses a method and apparatus for pose estimation, and an electronic device. A specific implementation of the method includes: obtaining an observation information sequence corresponding to a human target part, wherein the human target part comprises at least one of the following: a head and a hand; determining an initial human joint point feature based on the observation information sequence; and performing feature interaction based on the initial human joint point feature, and estimating a human pose using an interaction feature, so as to obtain human pose information. This implementation makes the estimated human pose more accurate and realistic.
    Type: Application
    Filed: July 19, 2024
    Publication date: January 23, 2025
    Inventors: Xiaozheng Zheng, Zhuo Su, Chao Wen, Zhou Xue
  • Publication number: 20250006700
    Abstract: A stacking structure including a first die and a second die bonded with the first die is provided. The first die has a first region and a second region encircled by the first region. The first die includes first metallization structures having a first seal ring structure and a first bonding structure having first dummy pads located over the first seal ring structure. The second die includes second metallization structures having a second seal ring structure and a second bonding structure having second dummy pads located over the second seal ring structure. The first die and the second die are bonded through bonding of the first and second bonding structures. The first and second seal ring structures are substantially vertically aligned, and the first dummy pads are respectively bonded with the second dummy pads.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Sheng Lin, Ning Jiang, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
  • Publication number: 20240427399
    Abstract: The disclosed technology is directed to a computing device for detecting and preventing melting of a component of the computing device. In some examples, the computing device includes a cable that connects a power supply unit and an add-on card, and a thermal protection controller. Based on a sensor signal from a temperature sensor of the cable, the thermal protection controller determines that a temperature associated with the cable exceeds a threshold temperature. Responsive to determining that the temperature associated with the cable exceeds the threshold temperature, the thermal protection controller causes the power supply unit to cease supplying power to the add-on card by transmitting an overtemperature signal through the cable.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Cheng-Yi Yang, Chien-Wei Chen
  • Patent number: 12176312
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: December 24, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Publication number: 20240419532
    Abstract: In some examples, a system detects disabling of a driver of a storage control feature included in a main processor of the system, where the storage control feature to manage access of a storage device. In response to detecting the disabling of the driver of the storage control feature included in the main processor, the system initiates a remediation action to prevent a fault in the system.
    Type: Application
    Filed: October 28, 2021
    Publication date: December 19, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Chien-Cheng Su
  • Publication number: 20240404991
    Abstract: Embodiments include methods of forming three-dimensional packages and the packages resulting therefrom. The packages may utilize a bridge die to electrically connect one die to another die and at least one additional die adjacent to the bridge die. The height-to-width ratio of the gap between the bridge die and the at least one additional die is controlled by thinning the bridge die to be thinner than the at least one additional die. The packages may utilize landing structures to adjoin a dielectric material of an attached die to a metallic landing structure of a base die.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Chao-Wen Shih, Min-Chien Hsiao, Kuo-Chiang Ting, Yen-Ming Chen, Ashish Kumar Sahoo, Chen-Sheng Lin, Hsin-Yu Pan
  • Patent number: 12154875
    Abstract: Provided is packages and method of fabricating the same. The package includes a first die, a second die, and an inductor. The second die is bonded to the first die through a bonding structure thereof. The inductor is located in the bonding structure. The inductor includes a spiral pattern parallel to top surfaces of the first die and the second die, and the spiral pattern includes at least a turn.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Tzuan-Horng Liu, Jen-Li Hu
  • Patent number: 12154897
    Abstract: A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240385672
    Abstract: In example implementations, an apparatus is provided. The apparatus includes an expansion slot, a peripheral device connected to the expansion slot, and a processor communicatively coupled to the expansion slot. The processor is to determine that a compatibility of the peripheral device with active state power management (ASPM) is unknown, provide a notification to indicate that the compatibility of the peripheral device with ASPM is unknown, wherein the notification provides a selection between disabling ASPM for the peripheral device or enabling ASPM for the peripheral device, and configure a basic input/output system (BIOS) setting in accordance with the selection to control the ASPM for the peripheral device.
    Type: Application
    Filed: October 13, 2021
    Publication date: November 21, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Chien-Cheng Su