Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967601
    Abstract: A bottom-emission light-emitting diode (LED) display includes a transparent substrate, a plurality of LEDs bonded on the substrate, a packaging layer formed on the substrate to cover the LEDs, and a reflecting layer formed on the packaging layer to reflect light emitted by the plurality of LEDs. The reflecting layer has a non-smooth shape or the packaging layer has different refractivities.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: April 23, 2024
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu, Chun-Bin Wen, Chien-Lin Lai, Hsing-Ying Lee
  • Publication number: 20240128635
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: December 24, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20240098818
    Abstract: A method and device for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The method stores, in a memory in at least one of the IMD or the EI, a base scanning schedule that defines a pattern for scanning windows over a scanning state. The method enters the scanning state during which a receiver scans for advertisement notices during the scanning windows. At least a portion of the scanning windows are grouped in a first segment of the scanning state. The method stores, in the memory, a scan reset pattern for restarting the scanning state. Further, the method automatically restarts the scanning state based on the scan reset pattern to form a pseudo-scanning schedule that differs from the base scanning schedule and establishes a communication session between the IMD and the EI.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Yongjian Wu, Jyoti Bhayana, Chao-Wen Young, Tejpal Singh, Samir Shah
  • Publication number: 20240085268
    Abstract: A device and method for measuring the decentration of optics under test is provided. The device comprises a rotational spindle for loading and rotating the optics under test, a light source module for providing incident light beam to the optics under test, and a wavefront sensor for receiving testing light beams with different exposures from the optics under test at a plurality of azimuthal directions.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 14, 2024
    Inventor: Chao-Wen Liang
  • Publication number: 20240088804
    Abstract: Provided is a motor braking device for a N-phase brushless motor. The motor braking device includes a switching circuit adapted to connect the N-phase brushless motor to a power supply, the switching circuit comprising a high side switch group and a low side switch group, each of the high side switch group and the low side switch group comprising N switching elements, and a control unit configured to control the switching circuit to brake the motor based on occurrence of a first event, the first event chosen from a group consisting of release of a trigger by a user, and occurrence of a predetermined condition as detected by a sensor. The control unit is configured to, upon occurrence of the first event, switch all the switching elements of one of the high side switch group or the low side switch group to an on-state, and simultaneously switch all the switching elements of the other one of the high side switch group and the lower side switch group to an off-state.
    Type: Application
    Filed: February 10, 2021
    Publication date: March 14, 2024
    Inventors: Bao An ZHANG, Zi Cong CHEN, Li Hua XIE, Chao WEN, Yong Min LI
  • Publication number: 20240079253
    Abstract: A transfer system adaptable to performing levelling alignment includes a transfer head that picks up micro devices, the transfer head having a plurality of pick-up heads protruded from a bottom surface of the transfer head; and a levelling fixture configured to perform levelling alignment for the transfer head, the levelling fixture having a plurality of cavities that are concave downwards to correspondingly accommodate the pick-up heads respectively.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 7, 2024
    Inventors: Biing-Seng Wu, Chun-Jen Weng, Chao-Wen Wu
  • Publication number: 20240071362
    Abstract: In example implementations, a computing device is provided. The computing device includes a system management bus, a controller communicatively coupled to the system management bus, a noise generating component communicatively coupled to the controller, a noise cancellation codec communicatively coupled to the system management bus, and a speaker communicatively coupled to the noise cancellation codec. The operating parameters of the noise generating component are provided to the controller. The noise cancellation codec is to receive the operating parameters of the noise generating component from the controller via the system management bus and to generate a noise cancellation signal based on the operating parameters. The speaker outputs the noise cancellation signal to cancel noise generated by the noise generating component.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Inventors: Chao-Wen Cheng, Tsung Yen Chen, Wen Shih Chen, Mo-Hsuan Lin, Juiching Chang
  • Patent number: 11916012
    Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11914541
    Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 27, 2024
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Wen Bin Lin, ChiWei Ding, Chun Yi Liu, Shuo-Cheng Cheng, Chao-Wen Cheng
  • Publication number: 20240055371
    Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.
    Type: Application
    Filed: January 9, 2023
    Publication date: February 15, 2024
    Inventors: Der-Chyang Yeh, Kuo-Chiang Ting, Yu-Hsiung Wang, Chao-Wen Shih, Sung-Feng Yeh, Ta Hao Sung, Cheng-Wei Huang, Yen-Ping Wang, Chang-Wen Huang, Sheng-Ta Lin, Li-Cheng Hu, Gao-Long Wu
  • Patent number: 11896831
    Abstract: Methods and devices for managing establishment of a communications link between an external instrument (EI) and an implantable medical device (IMD) are provided. The methods and devices comprise storing, in memory in at least one of the IMD or the EI an advertising schedule defining a pattern for advertisement notices. The advertisement notices are distributed un-evenly and separated by unequal advertisement intervals. The method transmits, from a transmitter in at least one of the IMD or the EI the advertisement notices. The advertisement notices are distributed as defined by the advertising schedule. The method establishes a communication session between the IMD and the EI.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: February 13, 2024
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Samir Shah, Heidi Hellman, Reza Shahandeh, Tejpal Singh, Youjing Huang, Chao-Wen Young
  • Publication number: 20240042892
    Abstract: Disclosed are an unlocking apparatus, a swapping device comprising same, and an unlocking control method. The unlocking apparatus is used for unlocking or locking a battery box in a battery bracket on an electric vehicle, and comprises a drive mechanism, an unlocking component, and a transmission member. The drive mechanism drives the unlocking component to move by means of the transmission member, so that the unlocking component drives a locking mechanism on the battery bracket to move to unlock or lock the battery box; the unlocking component is axially rotatable relative to the transmission member to adapt to the angle deviation between the unlocking component and the standard unlocking position on the battery bracket. The swapping device comprises the unlocking apparatus. In this way, even if there is a circumferential deviation, the unlocking component is ensured to be accurately aligned and connected.
    Type: Application
    Filed: July 6, 2021
    Publication date: February 8, 2024
    Inventors: Jianping Zhang, Yi Ji, Chao Wen, Yingfu Zhou
  • Publication number: 20240044529
    Abstract: A cooling distribution unit includes a main body, a removable unit and an adjustment mechanism. The main body includes a first guiding structure. The removable unit includes a casing, a pump and a second guiding structure. The first guiding structure and the second guiding structure are coupled with each other. The adjustment mechanism includes a guiding slot and a fulcrum part. The guiding slot has a front end and a rear end. A distance between a center of the front end of the guiding slot and the fulcrum part is greater than a distance between a center of the rear end of the guiding slot and the fulcrum part. While the removable unit is locked on the main body or detached from the main body, the first guiding structure or the second guiding structure is disposed within the guiding slot.
    Type: Application
    Filed: March 21, 2023
    Publication date: February 8, 2024
    Inventor: Chao-Wen Lu
  • Patent number: 11895829
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: February 6, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Rou Jiang, Chao-Wen Lay
  • Patent number: 11894299
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR LTD
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Patent number: 11894329
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Chao Wen Wang
  • Patent number: 11894309
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 11882690
    Abstract: The present disclosure provides a semiconductor structure having a bit line with a tapered configuration. The semiconductor structure includes: a substrate; a bit line structure, disposed over the substrate, wherein the bit line structure includes a cylindrical portion and a step portion above the cylindrical portion; a polysilicon layer, disposed over the substrate and around the bit line structure; and a landing pad, disposed over the polysilicon layer and the step portion.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Rou Jiang, Chao-Wen Lay
  • Fan
    Patent number: 11879475
    Abstract: A fan includes a motor base, a bearing, an impeller, a stator and a magnetic element. The motor base has a bearing stand in a center portion thereof. The impeller includes a metallic case, plural blades and a rotating shaft. A top surface of a top wall of the metallic case continuous with curved surface that defines part of a central opening, and a depth of the central opening is equal to a thickness of the top wall. The blades are disposed around an outer periphery of said metallic case. The rotating shaft is inserted into the central opening and penetrated through the bearing stand, wherein no raised ring structure is formed in the top wall, and the rotating shaft and the metallic case are jointed together by a laser welding process. The magnetic element is disposed on an inner wall of the metallic case and aligned with the stator.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chiu-Kung Chen, Chao-Wen Lu
  • Patent number: D1023107
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 16, 2024
    Inventor: Chao Wen