Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332983
    Abstract: A battery pack electrically comprising a temperature terminal and is configured such that when an external device is electrically connected to the battery pack, the device can detect the temperature of the battery pack, and the battery pack is further configured to receive a PWM signal from the external device when in the electrical connection state, and, on the basis of the PWM signal, determine the type and/or operating state of the external device. Also disclosed, a power tool system comprising the battery pack, as well as a communication system for the battery pack and the system. With the battery pack and the power tool system, it is possible to perform both a temperature sampling function and a function of identifying external device information only by a temperature terminal of the battery pack, thus same have the advantages of a simple and compact structure and low cost.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Inventors: Ye ZHANG, Ren Jie WANG, Chao WEN, Hai Bo MA
  • Patent number: 12094852
    Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240297151
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20240275686
    Abstract: An electrical appliance assembly for multiclient networking, comprising an electrical appliance and a battery unit, wherein the electrical appliance is configured to obtain electric energy from the battery unit or provide electric energy to the battery unit, wherein the electrical appliance, as a first client, comprises a first communication interface and a second communication interface, wherein the first communication interface is configured to communicate with a peripheral device, and the second communication interface is configured to communicate with the battery unit. The battery unit, as a second client, comprises a third communication interface and a fourth communication interface, wherein the third communication interface is configured to communicate with a peripheral device, and the fourth communication interface is configured to communicate with the electrical appliance.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 15, 2024
    Inventors: Xi GUO, Chao WEN, Hai Bo MA
  • Patent number: 12057437
    Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12057439
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 12057415
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Grant
    Filed: May 29, 2023
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Patent number: 12051673
    Abstract: A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12046579
    Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Hsien-Wei Chen, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 12025338
    Abstract: In some examples, an electronic device includes an audio output device, an airflow generator to generate an airflow, and a system controller to control an operational speed of the airflow generator. The electronic device further includes an audio controller to generate a noise cancellation audio output based on an indicator of the operational speed of the airflow generator provided from the system controller to the audio controller, and send the noise cancellation audio output to the audio output device to mitigate noise produced by the airflow generator.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: July 2, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Tsung-Yen Chen, Chien Fa Huang, Wen Shih Chen, Mo-Hsuan Lin
  • Patent number: 12015013
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20240194338
    Abstract: An auxiliary assessment method for cardiac function performed by a computing unit includes collecting a number of heartbeats and an amount of movement of a subject in a period of time; and calculating a distance per beat to assess cardiac function of the subject. The distance per beat is defined by dividing the amount of movement by the number of heartbeats. A length of the period of time is defined between at least two adjacent heartbeats. The amount of movement corresponds to a cumulative amount of movement in the period of time.
    Type: Application
    Filed: July 25, 2023
    Publication date: June 13, 2024
    Inventors: Chao-Wen CHEN, Hao-Yun KAO, Yu-Cheng CHUANG, Jo-Nan WU, Wen-Yen CHANG
  • Publication number: 20240194588
    Abstract: A semiconductor structure includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, a through substrate via (TSV) penetrating through the first semiconductor substrate and extending into the first interconnect structure, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the TSV through the first interconnect structure. The TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface, and the first bonding conductor includes a first bonding surface facing away the first interconnect structure. In a view, a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.
    Type: Application
    Filed: January 9, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 12009575
    Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Patent number: 11982500
    Abstract: A heat sink includes a heat conduction portion and a heat dissipation portion. The heat conduction portion is a flat plate with two main surfaces parallel with each other and a plurality of side surfaces. One of the two main surfaces is a contacting surface contacting a heat source. The heat dissipation portion is extended outward from at least one of the plurality of side surfaces of the heat conduction portion. The heat dissipation portion includes a plurality of first branches and a plurality of second branches. Each of the first branches is a flat plate and has two opposite main surfaces and four side surfaces. The two opposite main surfaces of each of the first branches are parallel to the two main surfaces of the heat conduction portion. The second branches are extended from the first branches and parallel to the heat conduction portion.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: May 14, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Chao-Wen Lu
  • Publication number: 20240153881
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Publication number: 20240136315
    Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventor: Chao Wen Wang
  • Publication number: 20240136280
    Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Chao-Wen Shih, Chen-Hua Yu, Han-Ping Pu, Hsin-Yu Pan, Hao-Yi Tsai, Sen-Kuei Hsu
  • Patent number: D1026988
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Inventor: Chao Wen
  • Patent number: D1037329
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: July 30, 2024
    Inventor: Chao Wen