Patents by Inventor Chao-Wen (Kevin) Chen

Chao-Wen (Kevin) Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTROL OF DEVICE FEATURES BASED ON SLOT CONFIGURATIONS
    Publication number: 20230315667
    Abstract: In example implementations, a computing device is provided. The computing device includes an expansion interface, a first device, a second device, and a processor communicatively coupled to the expansion interface. The expansion interface includes a plurality of slots. Two slots of the plurality of slots are controlled by a single reset signal. The first device is connected to a first slot of the two slots and has a feature that is compatible with the single reset signal. The second device is connected to a second slot of the two slots and does not have the feature compatible with the single reset signal. The process is to detect the first device connected to the first slot and the second device connected to the second slot and disable the feature by preventing the first slot and the second slot from receiving the single reset signal.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Wen Bin Lin, ChiWei Ding, Chun Yi Liu, Shuo-Cheng Cheng, Chao-Wen Cheng
  • Managing dynamic connection intervals for implantable and external devices
    Patent number: 11778674
    Abstract: A method, system and external instrument are provided. The method initiates a communication link between an external instrument (EI) and an implantable medical device (IMD), established a first connection interval for conveying data packets between the EI and IMD and monitors a connection criteria that includes at least one of a data throughput requirement. A battery indicator or link condition of the communications link is between the IMD and EI. The method further changes from the first connection interval to a second connection interval based on the connection criteria.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: October 3, 2023
    Assignee: Pacesetter, Inc.
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Xing Pei, Reza Shahandeh
  • SEMICONDUCTOR DEVICE HAVING ANTENNA AND MANUFACTURING METHOD THEREOF
    Publication number: 20230307391
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Application
    Filed: May 29, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Apparatuses exhibiting enhanced stress resistance and planarity, and related microelectronic devices and memory devices
    Patent number: 11769738
    Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Chao Wen Wang
  • Deep Neural Network Processing Device with Decompressing Module, Decompressing Method and Compressing Method
    Publication number: 20230289588
    Abstract: A deep neural network (DNN) processing device with a decompressing module, comprises a storage module, for storing a plurality of binary codes, a coding tree, a zero-point value and a scale; a decompressing module, coupled to the storage module, for generating a quantized weight array according to the plurality of binary codes, the coding tree and the zero-point value wherein the quantized weight array is generated according to an aligned quantized weight array and the zero-point value; and a DNN processing module, coupled to the decompressing module, for processing an input signal according to the quantized weight array and the scale.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: ALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Feng Huang, Jung-Hsuan Liu, Chao-Wen Lin
  • MAXIMIZATION OF SPEEDS IN MIXED MEMORY MODULE CONFIGURATIONS
    Publication number: 20230289302
    Abstract: In example implementations, a computing device is provided. The computing device includes a memory bus, a first memory module connected to a first slot of the memory bus, a second memory module connected to a second slot of the memory bus, and a processor communicatively coupled to the memory bus. The processor is to detect a mixed memory module configuration caused by the first memory module and the second memory module and train the first memory module and the second memory module to operate at a maximum mixed memory module configuration speed.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Wen-Bin Lin, Chao-Wen Cheng, Cheng-Yi Yang
  • Integrated devices in semiconductor packages and methods of forming same
    Patent number: 11749626
    Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Kai-Chiang Wu, Chung-Shi Liu, Shou Zen Chang, Chao-Wen Shih
  • BICYCLE TRAINER WITH HEIGHT ADJUSTING MEMBER
    Publication number: 20230271073
    Abstract: A bicycle trainer includes a base having a base portion and a standing portion, a supporting frame rotationally pivoted on the standing portion of the base around an axle, a cassette module mounted on the supporting frame and having multiple sprockets, and a flywheel module mounted on the supporting frame. A height adjusting member includes the standing portion, the supporting frame and a fixing element. The fixing element is placed in or between the standing portion and the supporting frame for keeping the supporting frame at a predetermined angle with respect to the standing portion.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Hsiao-Wen HSU, Jen-Chieh HUANG, Chao-Wen CHEN, Chin-Lai HUANG, Wen-Hai LO
  • Semiconductor packages
    Patent number: 11742297
    Abstract: A semiconductor package includes a first die, a plurality of second dies and a through via. The second dies are disposed over and electrically connected to the first die. The through via is disposed between the second dies and electrically connected to the first die. The through via includes a first portion having a first width and a second portion having a second width different from the first width and disposed between the first portion and the first die. The first portion includes a first seed layer and a first conductive layer, and the first seed layer is disposed aside an interface between the first portion and the second portion.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Method and apparatus of setting protection frames for protecting transmission of preamble punctured physical layer protocol data unit
    Patent number: 11737141
    Abstract: One wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets a request to send (RTS) frame, and controls the transmitter circuit to transmit the RTS frame via at least one channel excluding a preamble punctured channel. Another wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets an RTS frame, and controls the transmitter circuit to transmit the RTS frame via a plurality of channels including the preamble punctured channel.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: August 22, 2023
    Assignee: MEDIATEK INC.
    Inventors: Cheng-Yi Chang, Chao-Wen Chou, Kun-Sheng Huang, Chin-Chi Chang
  • PACKAGE STRUCTURE
    Publication number: 20230261361
    Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nan-Chin Chuang, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • SPEED SETTINGS FOR INTERFACES CONNECTED TO PREVIOUS GENERATION CARRIERS
    Publication number: 20230251865
    Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, a previous generation carrier connected to the interface, a controller communicatively coupled to the interface, and a basic input/output system (BIOS). The previous generation carrier includes a current generation memory card. The controller is to detect the previous generation carrier. The BIOS is to set the interface to operate at a speed associated with the previous generation carrier in response to detection of the previous generation carrier.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 10, 2023
    Inventors: CHAO-WEN CHENG, WEN SHIH CHEN, CHEN-PANG CHANG, YI-FENG LIN
  • Wafer on wafer bonding structure
    Patent number: 11715723
    Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • RISER CARDS WITH INLINE SLOTS
    Publication number: 20230240036
    Abstract: In example implementations, an apparatus is provided. The apparatus includes a riser card body, a first interface, a first 2×8 slot on a surface of the riser card body, and a second 2×8 slot on a same side of the surface of the riser card body as the first 2×8 slot. The first interface includes a first set of fingers and a second set of fingers at an end of the riser card body to connect to a peripheral component interconnect e×press (PC1e) slot of a motherboard. The first 2×8 slot and the second 2×8 slot are positioned perpendicular to the PCIe slot of the motherboard.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Inventors: Yu Lih Chuang, Yen-Tang Chang, Heather Louise Burnam Volesky, Jonathan D. Bassett, Wen Bin Lin, Chao-Wen Cheng
  • Chip package with antenna element
    Patent number: 11705411
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Yi-Che Chiang, Nien-Fang Wu, Min-Chien Hsiao, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Semiconductor device having antenna on chip package and manufacturing method thereof
    Patent number: 11705409
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Special Dual CTS Mode For Improvement In Collision Avoidance
    Publication number: 20230224963
    Abstract: Various techniques pertaining to a special dual clear-to-send (CTS) mode for improvement in collision avoidance in wireless communications are described. A first station (STA) transmits a request-to-send (RTS) and, in response, receives a first CTS from a second STA. The first STA waits to receive a second CTS from the second STA before transmitting data to the second STA responsive to the first CTS being of a first type and the second CTS being of a second type different from the first type. The first STA then transmits the data to the second STA upon passage of a waiting period.
    Type: Application
    Filed: November 14, 2022
    Publication date: July 13, 2023
    Inventors: Tsung-Hsuan Wu, Chao-Wen Chou, Ching-Yu Kuo, Ping Hsien Chiang, Ming-Yen Tsai
  • MICRO FAN
    Publication number: 20230216375
    Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes a plurality of axial induced coil units and a circuit board. The axial induced coil units are respectively preformed as a plurality of stator magnetic pole units, and are coupled to the circuit board. At least one of the coil units includes a coil and insulation material. The insulation material is block-shaped and covers at least a portion of the coil, and the central axis of the coil is parallel to the shaft of the rotor.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 6, 2023
    Inventors: Chin-Chun LAI, Chao-Wen LU
  • CONTROL OF A COOLING DEVICE IN A COMPUTING DEVICE
    Publication number: 20230213915
    Abstract: Examples for controlling an operating speed of a cooling device based on an operating mode of a processing unit, are described. In an example, a current value of a monitored current signal is determined. Based on the comparison of the current value with a predefined threshold value, a switch in an operating mode of the processing unit is determined. Thereafter, the computing device may be caused to increase the operating speed of the cooling device to a designated speed.
    Type: Application
    Filed: June 19, 2020
    Publication date: July 6, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Chao-Wen Cheng, Yu-Fan Chen, Mo-Hsuan Lin
  • METHOD AND DEVICE TO CONTROL COMMUNICATIONS POWER LEVEL
    Publication number: 20230209460
    Abstract: A method for managing power during communication with an implantable medical device, including establishing a communications link, utilizing a power corresponding to a session start power, to initiate a current session between an implantable medical device (IMD) and external device. A telemetry break condition of the communications link is monitored during the current session. The power utilized by the IMD is adjusted between low and high power levels, during the current session based on the telemetry break condition. The number of sessions is counted, including the current session and one or more prior sessions, in which the IMD utilized the higher power level, and a level for the session start power to be utilized to initiate a next session following the current session is adaptively learned based on the counting of the number of sessions.
    Type: Application
    Filed: March 3, 2023
    Publication date: June 29, 2023
    Inventors: Perry Li, Lequan Zhang, Xing Pei, Jeffery Crook, Yongjian Wu, Jun Yang, Chao-Wen Young