Abstract: The present application provides methods and systems for launching an unmanned aerial vehicle (UAV). An exemplary system for launching a UAV includes a detector configured to detect acceleration of the UAV in a launch mode. The exemplary system may also include a memory storing instructions and a processor configured to execute the instructions to cause the system to: obtain a signal configured to notify the UAV to enter the launch mode, determine whether the acceleration of the UAV satisfies a condition corresponding to threshold acceleration in the launch mode, and responsive to the determination that the acceleration of the UAV satisfies the condition, turn on a motor of the UAV.

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

Abstract: A semiconductor structure includes first and second semiconductor dies bonded together. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate, and a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure. The first bonding conductor extends from the first interconnect structure towards the through semiconductor via to electrically connect the first semiconductor die to the second semiconductor die.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: A support structure for a light-emitting diode utilizes the configuration of a sacrifice structure to achieve safe separation of a light-emitting diode from a carrier substrate. Specifically, when an external force is applied on the light-emitting diode or the carrier substrate, a breaking layer of the sacrifice structure is the first layer to be broken, so that the light-emitting diode and carrier substrate will become separated from each other.

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

Abstract: Semiconductor packages and method of forming the same are disclosed. One of the semiconductor packages includes a first die, a second die, a through via and a dielectric encapsulation. The second die is bonded to the first die. The through via is disposed aside the second die and electrically connected to the first die. The through via includes a step-shaped sidewall. The dielectric encapsulation encapsulates the second die and the through via.

Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Abstract: A fan includes a motor base, a bearing, an impeller, a stator and a magnetic element. The motor base has a bearing stand in a center portion thereof. The bearing is accommodated within the bearing stand. The impeller includes a metallic case, a hub, plural blades and a rotating shaft. The metallic case has a top wall and a sidewall. The hub is sheathed around the metallic case. The blades are disposed around an outer periphery of the hub. The rotating shaft is inserted into a central opening of the top wall and penetrated through the bearing stand, wherein no raised ring structure is formed in the top wall of the metallic case, and the rotating shaft and the metallic case are jointed together by a laser welding process. The magnetic element is disposed on an inner wall of the metallic case and aligned with the stator.

Abstract: A microLED display includes a first main substrate, microLEDs disposed above the first main substrate, a first light blocking layer disposed above the first main substrate to define emission areas, a light guiding layer disposed in the emission areas, and a plurality of connecting structures disposed in the emission areas respectively and electrically connected with the microLEDs.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

Abstract: In one example, touchpad assembly is disclosed, which may include a bottom cover, a horizontal elastic member flexibly positioned on the bottom cover, a balancing bar disposed on the bottom cover and substantially parallel to the horizontal elastic member, and a metal dome. The metal dome may include a first end fixedly connected to the bottom cover via a first fixture, and a second end to hold the horizontal elastic member and the balancing bar such that the balancing bar is flexibly engaged with the bottom cover. The balancing bar, the metal dome, and the horizontal elastic member may control a flexure of a touchpad when the touchpad is pressed.

Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.

Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes an axial induced coil unit and a circuit board. The axial induced coil unit is made by twining a coil in an axial direction for at least two layers and in a radial direction for at least two layers.

Abstract: A vacuum suction apparatus includes a semiconductor substrate with a top portion having grooves and a bottom portion having through holes, wherein each said groove correspondingly connects with at least one said through hole, and the groove has a width greater than a width of the through hole; and a cover plate disposed on a top surface of the semiconductor substrate. At least one edge of the vacuum suction apparatus has a vacuum chamber, which connects with the grooves. In another embodiment, the cover plate is replaced with a vacuum cover disposed above the semiconductor substrate, wherein the vacuum cover and the semiconductor substrate construct a vacuum chamber.