Patents by Inventor Chao Wen

Chao Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10875773
    Abstract: The present disclosure relates to a method for storage or transportation of graphene oxide. The method for storage or transportation of graphene oxide comprises the steps of: carrying out wet spinning of a graphene oxide spinning solution to a coagulating bath to obtain graphene oxide pellets; drying the obtained graphene oxide pellets; storing or transporting the dried graphene oxide pellets; and redispersing the stored or transported graphene oxide pellets.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: December 29, 2020
    Assignees: CORNELL UNIVERSITY, JMC CORPORATION
    Inventors: Yong Lak Joo, Chao-Wen Chang, Somayeh Zamani, Wonsik Jung, Taechung Kang, Sangjoon Park
  • Patent number: 10879197
    Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang
  • Publication number: 20200402868
    Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Publication number: 20200402960
    Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.
    Type: Application
    Filed: January 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Sung-Feng Yeh, Tzuan-Horng Liu, Chuan-An Cheng
  • Publication number: 20200402942
    Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.
    Type: Application
    Filed: April 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 10872842
    Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10867929
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 10867940
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 10867882
    Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10867966
    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Chao-Wen Shih
  • Publication number: 20200383053
    Abstract: A method for managing power during communication with an implantable medical device, including establishing a communications link, utilizing a power corresponding to a session start power, to initiate a current session between an implantable medical device (IMD) and external device. A telemetry break condition of the communications link is monitored during the current session. The power utilized by the IMD is adjusted between low and high power levels, during the current session based on the telemetry break condition. The number of sessions is counted, including the current session and one or more prior sessions, in which the IMD utilized the higher power level, and a level for the session start power to be utilized to initiate a next session following the current session is adaptively learned based on the counting of the number of sessions.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Perry Li, Lequan Zhang, Xing Pei, Jeffery Crook, Yongjian Wu, Jun Yang, Chao-Wen Young
  • Publication number: 20200381396
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Application
    Filed: September 3, 2019
    Publication date: December 3, 2020
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 10832978
    Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 10, 2020
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chao-Wen Wu
  • Publication number: 20200344825
    Abstract: A method, system and external instrument are provided. The method initiates a communication link between an external instrument (EI) and an implantable medical device (IMD), established a first connection interval for conveying data packets between the EI and IMD and monitors a connection criteria that includes at least one of a data throughput requirement. A battery indicator or link condition of the communications link is between the IMD and EI. The method further changes from the first connection interval to a second connection interval based on the connection criteria.
    Type: Application
    Filed: July 15, 2020
    Publication date: October 29, 2020
    Inventors: Yongjian Wu, Chao-Wen Young, Jun Yang, Xing Pei, Reza Shahandeh
  • Publication number: 20200343223
    Abstract: A package structure includes a first semiconductor die, a second semiconductor die, an insulating encapsulant and a redistribution layer. The first semiconductor die has first conductive posts and a first protection layer laterally surrounding the first conductive posts. The second semiconductor die is embedded in the first protection layer and surrounded by the first conductive posts of the first semiconductor die, wherein the second semiconductor die includes second conductive posts. The insulating encapsulant is encapsulating the first semiconductor die and the second semiconductor die. The redistribution layer is disposed on the insulating encapsulant and connected with the first conductive posts and the second conductive posts, wherein the first semiconductor die is electrically connected with the second semiconductor die through the first conductive posts, the redistribution layer and the second conductive posts.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Chao-Wen Shih
  • Publication number: 20200340496
    Abstract: In example implementations, an apparatus is provided. The apparatus includes an accelerometer, a plurality of fan blades, a coil magnet and a processor. The accelerometer is coupled to a motor to measure an amount of vibration. The plurality of fan blades is coupled to the motor. Each one of the plurality of fan blades comprises a magnet. The coil magnet is coupled to a fan housing that encloses the motor, the plurality of fan blades and the accelerometer. The processor is communicatively coupled to the motor, the accelerometer, and the coil magnet. The processor activates the coil magnet to control a balance of the plurality of fan blades in response to an amount of vibration measured by the accelerometer that exceeds a threshold.
    Type: Application
    Filed: January 19, 2018
    Publication date: October 29, 2020
    Inventors: AI-TSUNG LI, CHAO-WEN CHENG
  • Publication number: 20200335459
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Publication number: 20200335477
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20200325024
    Abstract: The present disclosure relates to a method for storage or transportation of graphene oxide. The method for storage or transportation of graphene oxide comprises the steps of: carrying out wet spinning of a graphene oxide spinning solution to a coagulating bath to obtain graphene oxide pellets; drying the obtained graphene oxide pellets; storing or transporting the dried graphene oxide pellets; and redispersing the stored or transported graphene oxide pellets.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Applicants: Cornell University, JMC Corporation
    Inventors: Yong Lak JOO, Chao-Wen CHANG, Somayeh ZAMANI, Wonsik JUNG, Taechung KANG, Sangjoon PARK
  • Patent number: 10804134
    Abstract: A vacuum transfer device includes a semiconductor substrate, which has a first hole disposed in a top portion of the semiconductor substrate; a nozzle disposed in a bottom portion of the semiconductor substrate and protruding downward, the nozzle being aligned with the first hole; and a second hole disposed through the nozzle and in the semiconductor substrate to meet the first hole.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 13, 2020
    Assignee: Prilit Optronics, Inc.
    Inventors: Biing-Seng Wu, Chun-Jen Weng, Chao-Wen Wu