Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.

Abstract: Example implementations relate to power supply controllers. In some examples, a controller can include instructions to: set a power threshold for a power supply coupled to a computing component when the computing component is operating in a first state, determine when the computing component is alternating from the first state to a second state, and allow the power supply to exceed the power threshold for a fixed period of time in response to the computing component alternating from the first state to the second state.

Abstract: A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes a plurality of axial induced coil units and a circuit board. The axial induced coil units are respectively preformed as a plurality of stator magnetic pole units, and are coupled to the circuit board. At least one of the coil units includes a coil and insulation material. The insulation material is block-shaped and covers at least a portion of the coil, and the central axis of the coil is parallel to the shaft of the rotor.

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.

Abstract: A semiconductor structure includes first and second semiconductor dies bonded together. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate, and a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure. The first bonding conductor extends from the first interconnect structure towards the through semiconductor via to electrically connect the first semiconductor die to the second semiconductor die.

Abstract: In one example, a device housing is described, which may include a base substrate and ion-exchanged glass beads disposed on an outer surface of the base substrate.

Abstract: A network for generating 3D shape includes a perceptual network and a Graphic Convolutional Network (GCN). The GCN includes a coarse shape generation network for generating a coarse shape, and a Multi-View Deformation Network (MDN) for refining the coarse shape. The MDN further comprises at least one MDN unit, which in turn comprises a deformation hypothesis sampling module, a cross-view perceptual feature pooling module and a deformation reasoning module. Systems and methods are also provided.

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer.

Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes an axial induced coil unit and a circuit board. The axial induced coil unit is made by twining a coil in an axial direction for at least two layers and in a radial direction for at least two layers.

Abstract: A network for generating 3D shape includes a perceptual network and a Graphic Convolutional Network (GCN). The GCN includes a coarse shape generation network for generating a coarse shape, and a Multi-View Deformation Network (MDN) for refining the coarse shape. The MDN further comprises at least one MDN unit, which in turn comprises a deformation hypothesis sampling module, a cross-view perceptual feature pooling module and a deformation reasoning module. Systems and methods are also provided.

Abstract: A light detection and ranging system comprises an optical transmitter for beam scanning on a scan region, and receiving reflected light from the scan region; and an optical receiver for directing the reflected light for signal conversion. The optical transmitter includes a beam refractive unit including optical refractive devices, rotatably disposed about a rotation axis, for directing a collimated laser beam from a first optical path towards a direction depending on rotation angles of the optical refractive devices; and a motion unit for actuating relative motion of the optical refractive devices so as to perform beam scanning towards directions on the scan region. The optical receiver includes an off-axis reflective unit, disposed in the first optical path, for directing the reflected light towards a second optical path; and a light detection unit, disposed in the second optical path, for performing signal conversion on the reflected light.

Abstract: A package includes an integrated circuit. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The second chip and the third chip are disposed side by side on the first chip. The second chip and the third chip are hybrid bonded to the first chip. The fourth chip is fusion bonded to at least one of the second chip and the third chip.

Abstract: Semiconductor packages and method of forming the same are disclosed. One of the semiconductor packages includes a first die, a second die, a through via and a dielectric encapsulation. The second die is bonded to the first die. The through via is disposed aside the second die and electrically connected to the first die. The through via includes a step-shaped sidewall. The dielectric encapsulation encapsulates the second die and the through via.

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.