Abstract: A display panel includes a drive backplane; a first electrode layer, including a plurality of first electrodes distributed in an array, where the first electrode includes a flat middle part and an edge part surrounding the middle part; a light-emitting function layer, at least partially covering the middle part; and a second electrode, covering the light-emitting function layer, and including a separating part and a plurality of flat parts separated by the separating part, where orthographic projections of the flat parts on the drive backplane are located in one-to-one correspondence within orthographic projections of the first electrodes on the drive backplane, the separating part includes a protruding area and a first recessed area connecting the protruding area and the flat part, and the protruding area is provided with a second recessed area recessed toward the drive backplane.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate electrode. The first nitride-based semiconductor layer includes at least two doped barrier regions defining an aperture between the doped barrier regions. The second nitride-based semiconductor layer is disposed over first nitride-based semiconductor layer. The third nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer and has a bandgap higher than a bandgap of the second nitride-based semiconductor layer. The passivation layer is disposed over the third nitride-based semiconductor layer, in which a vertical projection of the passivation layer on the first nitride-based semiconductor layer is spaced apart from the aperture. The gate insulator layer is disposed over the third nitride-based semiconductor layer.

Abstract: A magneto-resistive random access memory with segmented bottom electrode includes a magnetic tunnel junction pillar above a first portion of a bottom electrode layer, the first portion of the bottom electrode layer includes a metal region. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar and above a second portion of the bottom electrode layer including a metal-oxide region. The first portion of the bottom electrode layer composed of the metal region and the second portion of the bottom electrode layer composed of the metal-oxide region form the segmented bottom electrode.

Abstract: The present invention provides an SET8 lysine methyltransferase inhibitor and a preparation method and application thereof. The structural formula of the inhibitor is as follows: The inhibitor provided by the present invention has a significant inhibiting effect on lysine methyltransferase SET8 and the proliferation of tumor cells.

Abstract: The present invention relates to a Si-containing high-strength and low-modulus medical titanium alloy, and an additive manufacturing method and use thereof. The additive manufacturing method comprises alloy ingredient design, powder preparation, model construction and substrate preheating, and additive manufacturing molding; wherein the Si-containing high-strength and low-modulus medical titanium alloy is designed in the ingredient proportion of Ti 60-70 at. %, Nb 16-24 at. %, Zr 4-14 at. %, Ta 1-8 at. %, Si 0.1-5 at. %.

Abstract: A square bar grinding device includes a loading rack, a clamping device, a grinding device, and a grinding tool grinding device. The loading rack is provided with stations, the stations include a first station and a second station, the first station is used for placing a to-be-machined square bar, the grinding tool grinding device includes an oil stone assembly, the oil stone assembly is disposed at the second station, and the clamping device is used for clamping and transferring the to-be-machined square bar or the oil stone assembly in the stations of the loading rack to the grinding device. According to the square bar grinding device, a grinding tool grinding device is disposed at a loading rack, and can be clamped and transferred by a clamping device to be quickly moved to a grinding device for grinding of a grinding tool.

Abstract: A back-end-of-the-line (BEOL) interconnect structure is provided that includes a top via structure located on a metal line. An air gap is located adjacent to, and around, the metal line and top via structure. This air gap includes a lower portion adjacent to the metal line and an upper portion adjacent to the top via structure. Such an air gap can extend BEOL interconnect scaling for 2 nm technology node and below. Methods of forming such an BEOL interconnect structure are also provided.

Abstract: An electrical fuse for an integrated circuit (IC). The electrical fuse includes a dielectric material substrate, and at least one line of conducting material located in the dielectric material substrate. Each of the at least one line of conducting material includes a first conductive structure, a second conductive structure, and a fuse element extending horizontally between the first and second conductive structures. The fuse element has a height that is less than the height of the first and second conductive structures.

Abstract: A display panel, a method for preparing the same and a display apparatus are provided. The display panel includes: a base substrate, and a plurality of light-emitting devices at a side of the base substrate. The light-emitting devices each includes a first electrode. The first electrode includes: a reflection portion, and a cover portion at a side of the reflection portion facing away from the base substrate. The cover portion covers a front face and a side face of the reflection portion at the side of the reflection portion facing away from the base substrate. The cover portion includes: a first structural layer, and a second structural layer disposed between the first structural layer and the reflection portion. The second structural layer is configured to block the reflection portion from contacting the first structural layer.

Abstract: A magnetoresistive random access memory (MRAM) includes a pillar structure having a bottom electrode and a magnetic tunnel junction (MTJ) having a reference layer, a free layer and a tunnel barrier disposed between the reference layer and the free layer. The MTJ is disposed on the bottom electrode. A top electrode is disposed on the MTJ. The top electrode includes two or more tiers wherein each tier successively includes a smaller footprint.

Abstract: A metal-insulator-metal (MIM) capacitor includes a dielectric layer forming a plane and a capacitor dielectric formed in a pattern having a width parallel to the plane and a height transverse to the plane. Electrodes are formed as sidewall spacers on opposite sides of the width of the capacitor dielectric. Each of the electrodes has a contact to make an electrical connection to the electrode, the contact being disposed within the height.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A metal line is formed on a bottom liner, a sacrificial hardmask on a top surface of the metal line. Portions of the sacrificial hardmask are selectively removed that that do not correspond a desired location of a top via. The remaining sacrificial hardmask is replaced with the top via, the top via and the metal line each tapered such that a width at each respective bottom surface is greater than a width of each respective top surface.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack. A semiconductor device is provided. The semiconductor device including a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack, where the tunneling barrier comprises a center portion and two outer portions, where the center portion is on an upper horizontal portion of the reference layer, and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer. Forming a magnetic tunnel junction (MTJ) stack, where a tunneling barrier of the MTJ stack is wider than a reference layer of the MTJ stack.

Abstract: Aspects of the present invention provide a three-dimensional resistor with at least two horizontal resistive metal elements connected by at least one vertical resistive metal element. Each of the vertical resistive metal elements surrounds a portion of a first dielectric material where the portion of resistive metal surrounding the dielectric material forms a tube of the resistive metal. More than one vertical resistive metal element with a thickness between one and five nanometers can be present between each of two adjacent horizontal resistive metal elements.

Abstract: An antifuse structure including a first fuse conductor, a second fuse conductor in the same metallization level as the second fuse conductor, and a tapered fuse dielectric between and separating the first fuse conductor from the second fuse conductor.

Abstract: A semiconductor structure including a metal sidewall spacer arranged on a vertical sidewall of a dielectric pedestal, a fuse dielectric layer on top of the dielectric pedestal, and a conductive element on top of the fuse dielectric layer and directly above the metal sidewall spacer.

Abstract: A antifuse structure including a first metal sidewall spacer and a second metal sidewall spacer arranged on opposite sides of a tapered dielectric pedestal, and a fuse dielectric on top of the tapered dielectric pedestal and between the first metal sidewall spacer and the second metal sidewall spacer.

Abstract: A horizontal antifuse structure including a fuse dielectric layer, two slanted annular metal structures arranged adjacent to and opposite one another, wherein bottom portions of the two slanted annular metal structures are embedded in the fuse dielectric layer.

Abstract: A semiconductor device including a first stacked nanosheet Field Effect Transistor (FET), a second stacked nanosheet, a metal insulator metal (MIM) capacitor between the first stacked nanosheet and the second stacked nanosheet and an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet. An embodiment where the first stacked nanosheet and the second stacked nanosheet each include an upper stacked nanosheet and a lower stacked nanosheet, the upper stacked nanosheet and the lower stacked nanosheet each include alternating layers of a sacrificial material and a semiconductor channel material vertically aligned and stacked one on top of another. Forming a first stacked nanosheet, forming a second stacked nanosheet, forming a MIM capacitor between the first stacked nanosheet and the second stacked nanosheet and forming an insulator separating the MIM capacitor from each of the first stacked nanosheet and the second stacked nanosheet.