Patents by Inventor Chao Yang
Chao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12367374Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.Type: GrantFiled: April 13, 2022Date of Patent: July 22, 2025Assignee: NEUCHIPS CORPORATIONInventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
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Patent number: 12361873Abstract: Provided is a drive control circuit, which includes an input circuit (10), a first output circuit (11) and a second output circuit (12). An input circuit (10) is configured to control the potentials of a first node (N1) and a second node (N2) under the control of a signal input terminal (INT) and a clock signal terminal. The first output circuit (11) is configured to output a first power supply signal supplied by a first power supply line (VGH1) to a first output terminal (OUT1) under the control of a first node (N1), or to output a second power supply signal supplied by a second power supply line (VGL1) to the first output terminal (OUT1) under the control of a second node (N2).Type: GrantFiled: February 28, 2022Date of Patent: July 15, 2025Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Yanping Ren, Hongting Lu, Lian Xiang, Xingyu Chen, Chao Yang, Yan Yang
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Patent number: 12363913Abstract: A semiconductor device structure includes a metallization stack comprising one or more patterned metal layers. A bi-layer dielectric cap is disposed on and in contact with the metallization stack. At least one memory device is disposed on the bi-layer dielectric cap. A method for forming the metallization stack includes receiving a structure comprising a metallization layer and a first dielectric cap layer formed over the metallization layer. The metallization layer includes a logic area and a memory area. At least one memory stack is formed over the first dielectric cap layer. A self-assembled monolayer is formed over and in contact with the memory stack. A second dielectric cap layer is formed on and in contact with the first dielectric cap layer. The second dielectric cap layer is not formed on the self-assembled monolayer.Type: GrantFiled: July 13, 2023Date of Patent: July 15, 2025Assignee: International Business Machines CorporationInventors: Ashim Dutta, Ekmini Anuja De Silva, Chih-Chao Yang
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Publication number: 20250215469Abstract: The present invention provides a method for producing sesaminol or sesaminol glucosides comprising: reacting a protein with a substrate sesaminol glycoside having at least one glycosidic bond, and catalyzing the hydrolysis of the glycosidic bond; wherein, the protein is selected from the group consisting of the following (1) to (3): (1) a protein composed of the amino acid sequence SEQ ID NO: 1; (2) a protein composed of the amino acid sequence formed by deletion, substitution, insertion and/or addition of one or more amino acids in the amino acid sequence SEQ ID NO:1, wherein the protein has the activity of catalyzing the hydrolysis of the glycosidic bond; (3) a protein composed of an amino acid sequence having an sequence identity of more than 60% compared with the amino acid sequence of SEQ ID NO: 1, wherein the protein has the activity of catalyzing the hydrolysis of the glycosidic bond.Type: ApplicationFiled: December 27, 2024Publication date: July 3, 2025Inventors: NAN-WEI SU, YI-CHEN LO, CHANG-HUNG CHEN, CHAO-YANG HSU
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Patent number: 12344478Abstract: A transporting device can transport at least one product, the transporting device includes a mounting frame, a driving mechanism, a transmitting mechanism including a plurality of bent portions, a plurality of guiding mechanisms, and a supporting mechanism. Each guiding mechanism includes a rotating wheel and a guiding plate. Each bent portion is connected to the rotating wheel. The guiding plate is connected to the rotating wheel. The supporting mechanism can support the product. The driving mechanism is further connected to the rotating wheel and can drive the transmitting mechanism to rotate to drive the supporting mechanism to move. The driving mechanism is further connected to the guiding plate, the guiding plate and the rotating wheel can synchronously rotate to drive the supporting mechanism to pass through the bent portions. The present disclosure further provides a heating device.Type: GrantFiled: December 27, 2023Date of Patent: July 1, 2025Assignee: FU DING ELECTRONICAL TECHNOLOGY (JIASHAN) CO., LTD.Inventors: Huan Zhang, Qi Kuang, Hua Wan, Yi Liu, Wei-Wei Wu, Jing-Chao Yang, Wen-Jin Xia
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Publication number: 20250204001Abstract: A semiconductor device includes source/drain regions laterally disposed relative to one another in a row on a backside of the semiconductor device. A diffusion break is disposed between two adjacent source/drain regions and extends toward the backside between two source/drain region contacts. The diffusion break includes a different lateral dimension between the two adjacent source/drain regions than between the two source/drain region contacts.Type: ApplicationFiled: December 15, 2023Publication date: June 19, 2025Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Chih-Chao Yang
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Publication number: 20250189023Abstract: Disclosed is an auxiliary driving mechanism of a new energy vehicle, including a main motor, a reduction gear, a differential gear, an auxiliary motor, and a multi-speed gearbox. The multi-speed gearbox includes a housing, an auxiliary drive shaft, an intermediate shaft, and a connecting shaft, the auxiliary drive shaft is connected to the auxiliary motor, a plurality of first-stage reducing gear sets are arranged between the auxiliary drive shaft and the intermediate shaft, and a clutch is arranged on the auxiliary drive shaft; the clutch allows only one of the first-stage reducing gear sets to transmit the power of the auxiliary motor or disconnect the power between the auxiliary drive shaft and the intermediate shaft; a pair of transmission gear sets are arranged between the intermediate shaft and the connecting shaft.Type: ApplicationFiled: January 15, 2025Publication date: June 12, 2025Inventors: WENYONG YU, YANG ZHU, CHAO YANG, FENGLI HUANG
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Publication number: 20250191798Abstract: The present invention discloses a waste liquid recovery system for a large storage tank, and relates to the technical field of retirements of radioactive storage tanks. The present invention includes a control terminal, a transition tank, a water storage tank, a water-ring vacuum pump, a water mist separator, a high-pressure water spray apparatus, a solid waste collecting and weighing apparatus, and a sewage pump, where the transition tank and storage tank is connected with two ends of a recovery pipeline respectively; the water storage tank is provided with a ventilation valve, a solid-liquid separator, and a rotary stirring apparatus; the transition tank is connected to an inlet port of the solid-liquid separator; and a waste water outlet port of the water storage tank is connected with the sewage pump. According to the present invention, solid-liquid separation, a simple structure and a high automation degree are achieved.Type: ApplicationFiled: September 13, 2024Publication date: June 12, 2025Inventors: Kunlin MU, Fei LI, Changsheng HE, Zhouyang JIANG, Hao FAN, Qizhao MA, Bingzhi WANG, Tao WANG, Ya ZHOU, Kai XIE, Guangming DAI, Xiaoqiang LI, Yu LIU, Chao YANG, Li LI, Shaohan HOU
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Publication number: 20250194432Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack and a bottom electrode below the MTJ stack, where a portion of a bottom electrode is vertically aligned with a portion of the MTJ stack and a remaining portion of the bottom electrode extends horizontally beyond the MTJ stack. A semiconductor device including a MTJ stack and a bottom electrode below the MTJ stack, where a portion of a bottom electrode is vertically aligned with a portion of the MTJ stack and a remaining portion of the bottom electrode of the MTJ stack extends horizontally beyond the MTJ stack, where the bottom electrode comprises an interior void. A method including forming a MTJ stack on a sacrificial layer, a portion of a sacrificial layer is vertically aligned with a portion of the MTJ stack and a remaining portion of the sacrificial layer extends horizontally beyond the MTJ stack.Type: ApplicationFiled: December 12, 2023Publication date: June 12, 2025Inventors: Oscar van der Straten, Mark Lucarelli, Willie Lester Muchrison, JR., Chih-Chao Yang
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Publication number: 20250194168Abstract: A semiconductor structure including a single diffusion break (SDB) containing an airgap located between neighboring source/drain regions is provided. The airgap has an upper region that has a first width and a lower region that has a second width that is less than the first width. The airgap is pinched off on the backside of the structure in a region that is in close proximity to a backside interconnect structure. The presence of the airgap containing SDB can minimize capacitance as well as leakage of the structure.Type: ApplicationFiled: December 7, 2023Publication date: June 12, 2025Inventors: Tsung-Sheng Kang, Tao Li, Ruilong Xie, Chih-Chao Yang
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Patent number: 12327770Abstract: A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.Type: GrantFiled: November 29, 2021Date of Patent: June 10, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashim Dutta, Ruturaj Nandkumar Pujari, Saumya Sharma, Chih-Chao Yang
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Publication number: 20250183819Abstract: The present disclosure discloses a control method of tandem motors, relating to the technical field of motor control and solving problems of rotational speed synchronization, energy consumption and emergency protection of motors with axes connected in tandem. The control method includes: connecting axes of n motors in tandem, and collecting basic parameters of each motor; synthesizing a voltage space vector reference value; acquiring an expected voltage output vector; realizing the rotational speed synchronization and load balancing of the motors with the axes connected in tandem; and monitoring a working process of the motors with the axes connected in tandem in real time and solving the fault. The present disclosure greatly improves a collaboration ability of the motors, enhances fault detection and coping abilities and reduces resource consumption costs.Type: ApplicationFiled: December 27, 2024Publication date: June 5, 2025Inventors: WENYONG YU, ZHANGJIANG WANG, JIANHUA JIN, CHAO YANG, FENGLI HUANG
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Patent number: 12324358Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.Type: GrantFiled: December 1, 2021Date of Patent: June 3, 2025Assignee: International Business Machines CorporationInventors: Ashim Dutta, Lili Cheng, Chih-Chao Yang
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Patent number: 12315807Abstract: A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer.Type: GrantFiled: December 31, 2021Date of Patent: May 27, 2025Assignee: International Business Machines CorporationInventors: Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang
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Patent number: 12317752Abstract: A semiconductor structure may include a pyramidal magnetic tunnel junction on top of a bottom electrode, a tunnel layer on top and in electrical contact with the first magnetic layer, a second magnetic layer on top and in electrical contact with the tunnel layer, and a hard mask cap on top of the second magnetic layer. The pyramidal magnetic tunnel junction may have a first magnetic layer on top and in electrical contact with the bottom electrode. The semiconductor structure may include a first encapsulation spacer positioned along vertical sidewalls of the hard mask cap, a second encapsulation spacer positioned along vertical sidewalls of the second magnetic layer, a third encapsulation spacer positioned along vertical sidewalls of the tunnel layer, and a fourth encapsulation spacer positioned along vertical sidewalls of the first magnetic layer.Type: GrantFiled: May 12, 2021Date of Patent: May 27, 2025Assignee: International Business Machines CorporationInventors: Oscar van der Straten, Koichi Motoyama, Joseph F. Maniscalco, Chih-Chao Yang
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Publication number: 20250163694Abstract: A method for manufacturing a non-magnetic spatial latticed shell structure composed of carbon fiber plate members. The load-bearing member of the latticed shell structure is made of non-magnetic carbon fiber plate, and joints are made of non-magnetic titanium alloy material. The magnetic shielding layer is provided on the roofing system above the structural layer, and a non-magnetic space with a magnetic field strength lower than 1 nT is formed inside the structure. The load-bearing members are fixed by two carbon fiber limb plates in the form of inter-limb connection and forms an hollow rectangular built-up section; and the joint comprises a titanium alloy gusset plate, a titanium alloy bolt group, and a carbon fiber limb plate; the magnetic shielding layer of the roofing system comprises a shielding layer pad, a shielding layer, a shielding laminate, a buffer layer, a permalloy plate, and a batten.Type: ApplicationFiled: January 23, 2025Publication date: May 22, 2025Inventors: Yaozhi LUO, Huibin GE, Yuan CHENG, Chao YANG
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Publication number: 20250151532Abstract: A display panel includes a drive backplane; a first electrode layer, including a plurality of first electrodes distributed in an array, where the first electrode includes a flat middle part and an edge part surrounding the middle part; a light-emitting function layer, at least partially covering the middle part; and a second electrode, covering the light-emitting function layer, and including a separating part and a plurality of flat parts separated by the separating part, where orthographic projections of the flat parts on the drive backplane are located in one-to-one correspondence within orthographic projections of the first electrodes on the drive backplane, the separating part includes a protruding area and a first recessed area connecting the protruding area and the flat part, and the protruding area is provided with a second recessed area recessed toward the drive backplane.Type: ApplicationFiled: January 9, 2025Publication date: May 8, 2025Inventors: Yu WANG, Kuanta HUANG, Qing WANG, Yongfa DONG, Chao YANG, Shipeng LI, Hui TONG, Shangquan SHI, Xiong YUAN, Dongsheng LI, Xiaobin SHEN
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Patent number: 12289899Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate electrode. The first nitride-based semiconductor layer includes at least two doped barrier regions defining an aperture between the doped barrier regions. The second nitride-based semiconductor layer is disposed over first nitride-based semiconductor layer. The third nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer and has a bandgap higher than a bandgap of the second nitride-based semiconductor layer. The passivation layer is disposed over the third nitride-based semiconductor layer, in which a vertical projection of the passivation layer on the first nitride-based semiconductor layer is spaced apart from the aperture. The gate insulator layer is disposed over the third nitride-based semiconductor layer.Type: GrantFiled: December 17, 2021Date of Patent: April 29, 2025Assignee: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Chao Yang, Chunhua Zhou, Yong Liu, Qiyue Zhao, Jingyu Shen
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Patent number: D1077275Type: GrantFiled: June 20, 2023Date of Patent: May 27, 2025Assignee: NIO TECHNOLOGY (ANHUI) CO., LTDInventors: Fan Wu, Kechao Li, Jingyang Yao, Nikhil Banwaskar, Xiang Zhang, Yiqiang Sun, Chuangcheng Sun, Shiyi Hang, Yue Zhu, Jianwen Lai, Chao Yang
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Patent number: D1077276Type: GrantFiled: June 20, 2023Date of Patent: May 27, 2025Assignee: NIO TECHNOLOGY (ANHUI) CO., LTDInventors: Fan Wu, Kechao Li, Jingyang Yao, Nikhil Banwaskar, Xiang Zhang, Songhua Cao, Chuangcheng Sun, Shiyi Hang, Yue Zhu, Jianwen Lai, Chao Yang