Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Abstract: Compounds are provided as inhibitors of CXCR2, having the structure:

Abstract: A display device, an electronic apparatus and a method for manufacturing the display device are disclosed. The display device includes an array substrate and a first thin film encapsulation layer disposed on the array substrate. The array substrate is a silicon based organic light-emitting diode array substrate, and the array substrate includes a silicon substrate and a light-emitting device disposed on the silicon substrate; a second thin film encapsulation layer disposed between the light-emitting device and the first thin film encapsulation layer; and a color filter layer disposed between the first thin film encapsulation layer and the second thin film encapsulation layer, at each edge of the first thin film encapsulation layer, an orthographic projection of the array substrate on a plane parallel to the array substrate extends beyond an orthographic projection of the first thin film encapsulation layer on the plane.

Abstract: A vacuum apparatus includes process chambers, and a transfer chamber coupled to the process chambers. The transfer chamber includes one or more vacuum ports, thorough which a gas inside the transfer chamber is exhausted, and vent ports, from which a vent gas is supplied. The one or more vacuum ports and the vent ports are arranged such that air flows from at least one of the vent ports to the one or more vacuum ports are line-symmetric with respect to a center line of the transfer chamber.

Abstract: A toothed safe braking apparatus for use in robotic joint, comprising an electromagnetic telescoping apparatus (6) and a friction engagement component (10). The friction engagement component (10) is mounted on a shaft (C) of the robotic joint and comprises a brake lock ring gear (1) provided with a first center fitting hole (12), the brake lock ring gear (1) being provided with teeth (11) arranged on the outer circumferential surface thereof, a pretension ring (2) provided with a second center fitting hole (13), and a brake hub (4) provided with a first end surface (14), a second end surface (15), and an outer circumferential surface (16).

Abstract: A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.

Abstract: An interconnect structure includes a diffusion barrier layer disposed on exterior surfaces of an opening in a dielectric layer. A top surface of the diffusion barrier layer is below a top surface of the opening. A liner layer is disposed on a bottom surface and sidewalls of the diffusion barrier layer. A spacer layer is disposed on the top surface of the diffusion barrier layer and the liner layer and exposed sidewalls of the opening. An interconnect metal is disposed on the liner layer and the spacer layer. A metal cap is disposed on the interconnect metal.

Abstract: A semiconductor structure is presented including a device layer having a plurality of active devices, back-end-of-line (BEOL) components disposed under the device layer, a power distribution network (PDN) disposed over the device layer, and backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN. A through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL. An upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer to additional interconnects.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate electrode. The first nitride-based semiconductor layer includes at least two doped barrier regions defining an aperture between the doped barrier regions. The second nitride-based semiconductor layer is disposed over first nitride-based semiconductor layer. The third nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer and has a bandgap higher than a bandgap of the second nitride-based semiconductor layer. The passivation layer is disposed over the third nitride-based semiconductor layer, in which a vertical projection of the passivation layer on the first nitride-based semiconductor layer is spaced apart from the aperture. The gate insulator layer is disposed over the third nitride-based semiconductor layer.

Abstract: A semiconductor device including a magnetic tunnel junction (MTJ) stack vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode. A semiconductor device including a MTJ stack, vertically aligned between an annular shaped bottom electrode and an annular shaped top electrode, and an encapsulation layer surrounding vertical side surfaces of the MTJ stack, wherein the encapsulation layer does not surround the top electrode nor the bottom electrode. Forming a bottom electrode in a first inter-layer dielectric, forming a reference layer on the first inter-layer dielectric and on the bottom electrode, forming a tunnel barrier layer on the reference layer, forming a free layer on the tunnel barrier layer and patterning the reference layer, the tunnel barrier layer and the free layer into a magnetic tunnel function (MTJ) stack vertically aligned over the bottom electrode, while not patterning the bottom electrode nor the first inter-layer dielectric.

Abstract: The present invention relates to a Si-containing high-strength and low-modulus medical titanium alloy, and an additive manufacturing method and use thereof. The additive manufacturing method comprises alloy ingredient design, powder preparation, model construction and substrate preheating, and additive manufacturing molding; wherein the Si-containing high-strength and low-modulus medical titanium alloy is designed in the ingredient proportion of Ti 60-70 at. %, Nb 16-24 at. %, Zr 4-14 at. %, Ta 1-8 at. %, Si 0.1-5 at. %.

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A touch structure and a display panel are provided. The touch structure includes: first mesh electrodes extending in a first direction and second mesh electrodes extending in a second direction. The touch structure is absent in a window region. First mesh electrodes include at least one cross-window row separated by the window region, which includes a first cross-window row including: a first window mesh block adjacent to the window region and on a first side of the window region; a first conductive plate directly connected to mesh lines of the first window mesh block; and a first non-window mesh block on a side of the first window mesh block away from the window region; second mesh electrodes include at least one cross-window column including a first cross-window column which includes: a second window mesh block; a second conductive plate; and a second non-window mesh block.

Abstract: A light-emitting device comprises a substrate comprising a top surface; a plurality of light-emitting units formed on the top surface of the substrate comprising a first light-emitting unit, a second light-emitting unit, and one or a plurality of third light-emitting units, wherein each of the plurality of light-emitting units comprises a first semiconductor layer, an active layer and a second semiconductor layer; an insulating layer comprising a first insulating layer opening and a second insulating layer opening formed on each of the plurality of light-emitting units; a first extension electrode covering the first light-emitting unit, wherein the first extension electrode covers the first insulating layer opening on the first light-emitting unit without covering the second insulating layer opening on the first light-emitting unit; a second extension electrode covering the second light-emitting unit, wherein the second extension electrode covers the second insulating layer opening on the second light-emittin

Abstract: A robot joint, including: a housing; an output shaft, at least partially housed inside the housing and provided with a shaft portion and a flange portion at a first end of the shaft portion; a first bearing portion, housed in the housing and supporting a first position of the flange portion of the output shaft; a second bearing portion, housed in the housing and supporting a second position of the output shaft in an axial direction; and a motor, housed in the housing, where the second bearing portion is arranged between the motor and the first bearing portion along the axial direction of the output shaft. Further provided is a robot. By effectively supporting the output shaft at multiple points, the output shaft is enabled to more effectively and stably bear the moment or bending moment of a load, and the robot joint structure is enabled to be compact and lighter.

Abstract: A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.

Abstract: A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.

Abstract: A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

Abstract: Provided are a computer program product, system, and method for training and using a vector encoder to determine vectors for sub-images of text in an image to subject to optical character recognition. A vector encoder is trained to encode images representing text into vectors in a vector space. Vectors of images representing similar text have a high degree of cohesion in the vector space. Vectors of images representing dissimilar text have a low degree of cohesion in the vector space. An input image is processed to determine sub-images of the input image that bound text represented in the input image. The sub-images are inputted to the vector encoder to output sub-image vectors. The vector encoder generates a search vector for search text. Optical character recognition is applied to at least one region of the input image including the sub-images having sub-image vectors matching the search vector.

Abstract: A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.