Patents by Inventor Chao Yi
Chao Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411331Abstract: A power supply device includes a power supply housing having an accommodating space and an accommodating opening, a hybrid wire-to-wire connector structure and a circuit board disposed in the accommodating space. The hybrid wire-to-wire connector structure includes a connecting seat and an adapter seat. The connecting seat has a signal line terminal and a power line terminal. The connecting seat is disposed in the accommodating opening through an annular rib. The adapter seat has a signal conduction end and a power conduction end. The adapter seat has formed a hook corresponding to the annular rib. The connecting seat and the adapter seat are combined through the signal conduction end inserted in the signal line terminal, the power conduction end inserted in the power line terminal and the hook clamped with the annular rib. Therefore, the power and signal connectors are integrated so as to simplify the assembly.Type: GrantFiled: June 14, 2019Date of Patent: August 9, 2022Assignee: CHICONY POWER TECHNOLOGY CO., LTD.Inventors: Cheng-Chan Wu, Chao-Yi Huang, Hung-Chieh Lin
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Patent number: 11274065Abstract: An inorganic felt material includes zirconia stabilized by at least one Group IIA material, such that the Group IIA material includes at least one of calcium (Ca), magnesium (Mg), or a combination thereof. The felt material may also include at least one Group III material.Type: GrantFiled: June 13, 2018Date of Patent: March 15, 2022Assignee: FuelCell Energy, Inc.Inventors: Matthew T. Snider, Chao-yi Yuh
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Publication number: 20220077094Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.Type: ApplicationFiled: November 12, 2021Publication date: March 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
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Patent number: 11205795Abstract: A reinforced electrolyte matrix for a molten carbonate fuel cell includes a porous ceramic matrix, a molten carbonate salt provided in the porous ceramic matrix, and at least one reinforcing structure comprised of at least one of yttrium, zirconium, cerium or oxides thereof. The reinforcing structure does not react with the molten carbonate salt. The reinforced electrolyte matrix separates a porous anode and a porous cathode in the molten carbonate fuel cell.Type: GrantFiled: November 21, 2016Date of Patent: December 21, 2021Assignee: FuelCell Energy, Inc.Inventors: Arun Surendranath, Abdelkader Hilmi, Chao-Yi Yuh
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Publication number: 20210388046Abstract: A chimeric signal peptide for protein expression includes an N-region, a hydrophobic region, and a C-region, wherein the N-region and the C-region are from a same signal peptide of a first protein and the hydrophobic region is from a signal peptide of a second protein, wherein the first protein is different from the second protein. The first and second protein are independently selected from the group consisting of BM40, IL2, HA, Insulin, CD33, IFNA2, IgGK leader, AZU, and SEAP.Type: ApplicationFiled: December 23, 2019Publication date: December 16, 2021Applicant: Development Center for BiotechnologyInventors: Chao-Yi TENG, Ying-Ju CHEN
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Patent number: 11197610Abstract: The present invention discloses a smart terminal and a smart wrist watch.Type: GrantFiled: July 8, 2016Date of Patent: December 14, 2021Assignee: GOERTEK INC.Inventors: Lin Wang, Peijie Zhao, Jianguo Zhang, Chao Yi
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Patent number: 11196824Abstract: A method for controlling functions of an electronic device by a server includes establishing a communication connection between the server and the electronic device when a distance between the electronic device and the server is less than or equal to a preset value. Positioning information of the electronic device is acquired at every preset time when the electronic device enters a preset control area. A control mode of the electronic device is determined according to positioning information of the electronic device. Once a control signal is generated according to the control mode of the electronic device, status of an image-capturing device, and/or status of a microphone of the electronic device are controlled according to the control signal.Type: GrantFiled: January 20, 2020Date of Patent: December 7, 2021Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Shuang-Feng Tao, Chao-Yi Ke, Jun Zhang
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Patent number: 11177228Abstract: A semiconductor device comprises a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump over the conductive pad, a conductive cap over the conductive bump, and a passivation layer over the semiconductor substrate and surrounding the conductive bump. A combination of the conductive bump and the conductive cap has a stepped sidewall profile. The passivation layer has an inner sidewall at least partially facing and spaced apart from an outer sidewall of the conductive bump.Type: GrantFiled: June 10, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
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Publication number: 20210351131Abstract: A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Applicant: Winbond Electronics Corp.Inventors: Chia-Jung Chuang, Isao Tanaka, Yung-Wen Hung, Chao-Yi Huang
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Publication number: 20210351139Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
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Patent number: 11140451Abstract: In some embodiments, a method maps attributes of metadata for a plurality of content instances to metadata nodes. The metadata nodes are connected to type nodes that define a type of metadata for each metadata node and a respective content node for a respective content instance. The method generates a plurality of sample paths using the content nodes, the metadata nodes, and the type nodes from the mapping of attributes of the metadata. A similarity of content nodes is analyzed using the plurality of sample paths. Then, the method generates a representation of each of the plurality of content instances using the similarity of the content nodes. The representation represents the similarity between content instances in the plurality of content instances.Type: GrantFiled: August 7, 2019Date of Patent: October 5, 2021Assignee: HULU, LLCInventors: Fanding Li, Xiaohui Xie, Jing Ruan, Chao Yi
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Publication number: 20210304432Abstract: An image analysis method includes: inputting a to-be analyzed image into a region-based convolutional neural network (RCNN) model; outputting a masked image; calculating the center of a masked object in the masked image using the region-based convolutional neural network model; calculating the center of a masked object in the masked image; regarding the center as a origin of coordinate, searching for the farthest coordinate point from the origin of coordinate in each of the four quadrants relative to the origin of coordinate; generating an image analysis block for each of the farthest coordinate points; and performing post-processing on the image analysis blocks to obtain an object range.Type: ApplicationFiled: March 23, 2021Publication date: September 30, 2021Applicant: Winbond Electronics Corp.Inventors: Tung-Yu WU, Chun-Yen LIAO, Chun-Sheng WU, Kao-Tsair TSAI, Chao-Yi HUANG
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Patent number: 11127703Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.Type: GrantFiled: April 2, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
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Publication number: 20210288491Abstract: A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal: a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.Type: ApplicationFiled: September 5, 2016Publication date: September 16, 2021Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.Inventors: Kueir-Liang LU, Lei SHI, Chao Yi CHANG, Chuan Fang CHIN
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Publication number: 20210280126Abstract: The disclosure provides a display device and a driving method thereof. The display device includes a light emitting module and a display panel. The light emitting module includes an optical sensor and multiple light emitting diodes (LEDs). The LEDs are adjacent to the optical sensor. The LEDs emit red, green, and blue light. The LEDs dynamically convert brightness of the red, green, and blue light. The display panel is disposed on the light emitting module. The display device of the disclosure may achieve a full-screen display or have a higher resolution.Type: ApplicationFiled: February 19, 2021Publication date: September 9, 2021Applicant: Innolux CorporationInventors: Chao-Yi Hung, Minghuei Wang
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Patent number: 11114380Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.Type: GrantFiled: September 16, 2019Date of Patent: September 7, 2021Assignee: Winbond Electronics Corp.Inventors: Chia-Jung Chuang, Isao Tanaka, Yung-Wen Hung, Chao-Yi Huang
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Publication number: 20210262718Abstract: A refrigerator includes a cabinet structure having a refrigerator compartment and a freezer compartment. An evaporator is positioned in the freezer compartment within an evaporator housing. A door is pivotally coupled to the cabinet structure for selectively providing access to the refrigerator compartment and includes an ice maker. A duct assembly includes an ice maker feed duct operably coupled to the evaporator housing at a first end, and further coupled to the ice maker at a second end. The duct assembly further includes an ice maker return duct operably coupled to the ice maker at a first end and further coupled to the evaporator housing at a second end. First and second fans are provided in-series, wherein the first fan provides cooled air to the freezer compartment, and the second fan provides cooled air from the first fan to the ice maker during an ice making cycle.Type: ApplicationFiled: February 25, 2020Publication date: August 26, 2021Applicant: WHIRLPOOL CORPORATIONInventors: Daniel W. Burlingham, Chao-Yi Chen, Milind Devle, Rishikesh Vinayak Kulkarni, Mahalingappa Mulimani, E. C. Pickles, Richard A. Spletzer, Yan Zhang, Benjamin G. Jimenez, Vishal S. Marathe
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Patent number: 11081459Abstract: A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.Type: GrantFiled: October 7, 2019Date of Patent: August 3, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Yu Ku, Hon-Lin Huang, Chao-Yi Wang, Chen-Shien Chen, Chien-Hung Kuo
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SUPPORTED NICKEL CATALYSTS USED AS DIRECT INTERNAL REFORMING CATALYST IN MOLTEN CARBONATE FUEL CELLS
Publication number: 20210234181Abstract: Disclosed here is a supported catalyst comprising a thermally stable core, wherein the thermally stable core comprises a metal oxide support and nickel disposed in the metal oxide support, wherein the metal oxide support comprises at least one base metal oxide and at least one transition metal oxide or rare earth metal oxide mixed with or dispersed in the base metal oxide. Optionally the supported catalyst can further comprise an electrolyte removing layer coating the thermally stable core and/or an electrolyte repelling layer coating the electrolyte removing layer, wherein the electrolyte removing layer comprises at least one metal oxide, and wherein the electrolyte repelling layer comprises at least one of graphite, metal carbide and metal nitride. Also disclosed is a molten carbonate fuel cell comprising the supported catalyst as a direct internal reforming catalyst.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Jin-Yun WANG, Mohammad FAROOQUE, Ramakrishnan VENKATARAMAN, Chao-Yi YUH, April CORPUZ -
Patent number: 11075173Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.Type: GrantFiled: October 10, 2019Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii