Abstract: Techniques for generating opinion-based content responsive to a user input are described. The system may receive a user input, and determine dialog context data corresponding to a dialog between a user and the system, and including the user input. The system may determine generation of content responsive to the user input requires opinion-based knowledge, and may extract entities from the dialog context data, and determine natural language data of a knowledge base that includes entities similar to the extracted entities. The system may processes the natural language data and the dialog context data to determine a subset of the natural language data that is responsive to the user input. The system may generate output data responsive to the user input using the responsive natural language data and the dialog context.

Abstract: The present application discloses a bulk acoustic wave resonance assembly and a method for manufacturing the same. The bulk acoustic wave resonance assembly of the present application includes a substrate, a first resonance assembly and a second resonance assembly which are arranged on the substrate; an interconnection region is formed between the first resonance assembly and the second resonance assembly; the first resonance assembly includes a first bottom electrode, a first piezoelectric layer, and a first top electrode which are arranged on the substrate in sequence; the second resonance assembly includes a second bottom electrode, a second piezoelectric layer, and a second top electrode which are arranged on the substrate in sequence; the first bottom electrode and the second top electrode are connected to each other in the interconnection region; and the second bottom electrode and the first top electrode are connected to each other in the interconnection region.

Abstract: Provided are a new class of hydrazone amide derivatives and the use thereof in the preparation of anti-osteoporosis drugs, wherein the structural formula of the hydrazone amide derivative is as shown in formula (I), and same are a new class of compounds with an anti-osteoporosis effect.

Abstract: Disclosed is a sub-sampling phase-locked loop circuit capable of avoiding harmonic locking, which comprises a harmonic suppression sampling charge pump module, a filter module and a voltage-controlled oscillator module; a reference clock signal and differential signals are respectively accessed to an input end of the harmonic suppression sampling charge pump module, an output signal of an output end of the harmonic suppression sampling charge pump module is accessed to a filter and then accessed to an input of a voltage-controlled oscillator, an output end of the voltage-controlled oscillator module outputs differential signals as the differential signals accessed to the input end of the harmonic suppression sampling charge pump module, output signals of the voltage-controlled oscillator module are used as final outputs of the phase-locked loop circuit, and the output differential signals are synchronous with the reference clock in phase at the same time.

Abstract: A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Abstract: The present invention describes a water based semi-synthetic metal working fluid comprising a base oil, an organic acid, emulsifiers, a concentrate additive, water and a microbial growth control agent which comprises an alky alcohol amine.

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

Abstract: The current invention relates to a novel class of alkyl alcohol amines where the amine is a primary amine. Embodiments relate to a method of controlling microbial growth in metal working fluids, comprising adding such an alkyl alcohol amine to the metal working fluid. Other embodiments relate to semi-synthetic metal working fluid compositions which include the microbial growth control agent comprising this particular class of alkyl alcohol amines.

Abstract: Prodrugs and derivatives of anesthetics (e.g., capsaicin, bupivacaine) and methods of using the same.

Abstract: A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

Abstract: Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.

Abstract: A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Abstract: Disclosed is a sub-sampling phase-locked loop circuit capable of avoiding harmonic locking, which comprises a harmonic suppression sampling charge pump module, a filter module and a voltage-controlled oscillator module; a reference clock signal and differential signals are respectively accessed to an input end of the harmonic suppression sampling charge pump module, an output signal of an output end of the harmonic suppression sampling charge pump module is accessed to a filter and then accessed to an input of a voltage-controlled oscillator, an output end of the voltage-controlled oscillator module outputs differential signals as the differential signals accessed to the input end of the harmonic suppression sampling charge pump module, output signals of the voltage-controlled oscillator module are used as final outputs of the phase-locked loop circuit, and the output differential signals are synchronous with the reference clock in phase at the same time.

Abstract: A phase-locked loop circuit comprises a clock signal loss detection module, a time-to-digital converter, a digital-to-time converter, a phase discriminator, a charge pump, a loop filter, a comparator, a voltage-controlled oscillator, a frequency divider, a reference voltage generation module and a switch; a capacitor array of the voltage-controlled oscillator is adjusted by using an output of the comparator, so that a control voltage Vctrl of the voltage-controlled oscillator is constantly equal to a reference voltage after a phase-locked loop is locked and does not change along with a change of a PVT condition; after a reference clock signal is lost, the circuit directly adopts the reference voltage as the control voltage of the voltage-controlled oscillator, and after the reference clock signal is re-accessed, an output delay of the digital-to-time converter is adjusted, clock edge alignment of a new reference clock signal and a feedback clock signal is realized.

Abstract: A phase-locked loop circuit comprises a clock signal loss detection module, a time-to-digital converter, a digital-to-time converter, a phase discriminator, a charge pump, a loop filter, a comparator, a voltage-controlled oscillator, a frequency divider, a reference voltage generation module and a switch; a capacitor array of the voltage-controlled oscillator is adjusted by using an output of the comparator, so that a control voltage Vctrl of the voltage-controlled oscillator is constantly equal to a reference voltage after a phase-locked loop is locked and does not change along with a change of a PVT condition; after a reference clock signal is lost, the circuit directly adopts the reference voltage as the control voltage of the voltage-controlled oscillator, and after the reference clock signal is re-accessed, an output delay of the digital-to-time converter is adjusted, clock edge alignment of a new reference clock signal and a feedback clock signal is realized.

Abstract: The present application falls within the technical field of additives for metalworking fluids and specifically relates to a phenolamine additive, a preparation method, and use thereof. The phenolamine additive comprises a compound of Formula (1), a compound of Formula (2), a compound of Formula (3), a compound of Formula (4), and a compound of Formula (5), which has the characteristics of good antimicrobial performance and high stability, and does not produce any sedimentation and precipitation when compounded into a metalworking fluid.

Abstract: A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.

Abstract: The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

Abstract: Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.