Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190229126
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Patent number: 10355008
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 10269819
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Publication number: 20190043884
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 7, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Publication number: 20180350827
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: May 15, 2018
    Publication date: December 6, 2018
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 10090318
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Patent number: 9991273
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20180040626
    Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Hongbin Zhu, Charles H. Dennison, Gordon A. Haller, Merri L. Carlson, John D. Hopkins, Jia Hui Ng, Jie Sun
  • Publication number: 20170365615
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9793282
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 17, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9754952
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20170229470
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Application
    Filed: April 25, 2017
    Publication date: August 10, 2017
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Patent number: 9659949
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: May 23, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Patent number: 9557376
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20160284719
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Inventors: Hongbin Zhu, Gordon A. Haller, Charles H. Dennison, Anish A. Khandekar, Brett D. Lowe, Lining He, Brian Cleereman
  • Publication number: 20160195581
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Patent number: 9287184
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland
  • Publication number: 20160049417
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Patent number: 9184175
    Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Akira Goda, John Hopkins, Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20150170979
    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Kenneth W. Marr, Deepak Thimmegowda, Philip J. Ireland