Patents by Inventor Charles H. Dennison

Charles H. Dennison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7871934
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: January 18, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Charles H. Dennison, Trung T. Doan
  • Patent number: 7838341
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 23, 2010
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7803655
    Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: September 28, 2010
    Assignee: Ovonyx, Inc.
    Inventors: Brian G. Johnson, Charles H. Dennison
  • Patent number: 7804082
    Abstract: A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: September 28, 2010
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Publication number: 20100200829
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Application
    Filed: April 21, 2010
    Publication date: August 12, 2010
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Publication number: 20100197120
    Abstract: A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.
    Type: Application
    Filed: April 8, 2010
    Publication date: August 5, 2010
    Inventors: Fabio Pellizzer, Charles H. Dennison
  • Publication number: 20100163825
    Abstract: A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: STMICROELECTRONICS, S.r.l.
    Inventors: Charles H. Dennison, George A. Gordon, John M. Peters
  • Patent number: 7729162
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 1, 2010
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 7728352
    Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: June 1, 2010
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Publication number: 20100019388
    Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices eliminating the need for precise mask alignment and allowing the etching of the contact hole controlled independent of the etching of the interconnect trough that may be repeated during the formation of multilevel integrated circuits. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 28, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Charles H. Dennison, Trung T. Doan
  • Publication number: 20090230505
    Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Inventor: Charles H. Dennison
  • Patent number: 7572666
    Abstract: A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: August 11, 2009
    Inventors: Charles H. Dennison, Alice T. Wang, Kanaiyalal Chaturbhai Patel, Jenn C. Chow
  • Patent number: 7569485
    Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Charles H Dennison, Trung T. Doan
  • Publication number: 20090091971
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Patent number: 7491574
    Abstract: A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventor: Charles H. Dennison
  • Publication number: 20080246161
    Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 9, 2008
    Inventor: Charles H. Dennison
  • Publication number: 20080177943
    Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
    Type: Application
    Filed: February 12, 2008
    Publication date: July 24, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Brian M. Shirley, Charles H. Dennison, Kevin J. Ryan
  • Patent number: 7399655
    Abstract: A damascene approach may be utilized to form an electrode to a lower conductive line in a phase change memory. The phase change memory may be formed of a plurality of isolated memory cells, each including a phase change memory threshold switch and a phase change memory storage element.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: July 15, 2008
    Assignee: Ovonyx, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 7390691
    Abstract: A phase change memory with higher column landing margin may be formed. In one approach, the column landing margin may be increased by increasing the height of an electrode. For example, the electrode being made of two disparate materials, one of which includes nitride and the other of which does not. In another approach, a hard mask is used which is of substantially the same material as an overlying and surrounding insulator. The hard mask and an underlying phase change material are protected by a sidewall spacer of a different material than the hard mask. If the hard mask and the insulator have substantially the same etch characteristics, the hard mask may be removed while maintaining the protective character of the sidewall spacer.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Charles H. Dennison, Ilya V. Karpov
  • Patent number: RE40790
    Abstract: A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first co
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: June 23, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Guy T. Blalock