Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

Abstract: Plating bath and well structures and methods are described to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing up the reservoir wall. An electroplating apparatus includes a vessel holding a liquid solution including metal plating material and an organic species, and a method of operating an electroplating apparatus. The apparatus is designed with plating bath and structures and methods to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing or wicking up the inner surfaces of reservoir walls, and to wash them back down on a continuous or cyclical basis in order to maintain a concentration of organic compounds in the plating solution within upper and lower specification limits.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

Abstract: A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

Abstract: A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer.

Abstract: A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver.

Abstract: A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer.

Abstract: A chemical bath system includes a reactor tank configured to store a chemical bath solution including at least one organic element, and an organics removing chamber assembly. The organics removing chamber assembly includes at least one sub-chamber that delivers the chemical bath solution from a high-pressure section of a bath circuit to a low-pressure section. The organics removing chamber assembly modifies an amount of the at least one organic element as the chemical bath solution flows therethrough. The chemical bath system further includes an analysis/dosing controller. The analysis/dosing controller outputs a control signal that controls the organics removing chamber assembly to modify the amount of the at least one organic element in the chemical bath solution based on a comparison between an actual amount of the at least one organic element in the chemical bath solution and a desired amount of the at least one organic element.

Abstract: A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.