Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photonics chips and methods of manufacture. A structure includes: a photonics chip having a grated optical coupler; an interposer attached to the photonics chip, the interposer having a grated optical coupler; an optical epoxy material provided between the grated optical coupler of the photonics chip and the grated optical coupler of the interposer; and epoxy underfill material provided at interstitial regions between the photonics chip and the interposer which lie outside of an area of the grated optical couplers of the photonics chip and the interposer.

Abstract: Plating bath and well structures and methods are described to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing up the reservoir wall. An electroplating apparatus includes a vessel holding a liquid solution including metal plating material and an organic species, and a method of operating an electroplating apparatus. The apparatus is designed with plating bath and structures and methods to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing or wicking up the inner surfaces of reservoir walls, and to wash them back down on a continuous or cyclical basis in order to maintain a concentration of organic compounds in the plating solution within upper and lower specification limits.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A method is presented for collecting and removing radon from a confined area, a storage box or articles of clothing. The method includes collecting radon from the confined area or around a storage box via at least one collector, connecting each of a plurality of radon adsorbers to a corresponding power supply or power source such as a battery, capacitor, fuel cell, etc. diverting, via a plurality of valves, the collected radon or radon daughters through one or more of the plurality of radon adsorbers, and receiving, via a plurality of radon storage units, radon or radon daughters held by the plurality of radon adsorbers for a predetermined period of time.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer.

Abstract: A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide.

Abstract: A plating product fabrication method includes forming a first concentrate. The concentrate includes a metal species, such as Tin, and a trace amount of an alpha emitting species, such as Polonium. The plating product fabrication method also includes creating a circuit between a filtering anode and a filtering cathode and reducing the alpha emitting species from the concentrate by plating the alpha emitting species upon the filtering cathode. In this manner, a purified concentrate is formed. The purified concentrate may be utilized to plate the metal species upon a plating cathode. The purified concentrate may be utilized to form a purified metal species.

Abstract: A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with a hollow core of the first conductive layer.

Abstract: A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al—Cu) layer over a dielectric layer; and depositing an aluminum-chromium (Al—Cr) layer directly over the Al—Cu layer.

Abstract: A method is presented for collecting and removing radon from a confined area, a storage box or articles of clothing. The method includes collecting radon from the confined area or around a storage box via at least one collector, connecting each of a plurality of radon adsorbers to a corresponding power supply or power source such as a battery, capacitor, fuel cell, etc. diverting, via a plurality of valves, the collected radon or radon daughters through one or more of the plurality of radon adsorbers, and receiving, via a plurality of radon storage units, radon or radon daughters held by the plurality of radon adsorbers for a predetermined period of time.

Abstract: A method is presented for collecting and removing radon from a confined area, a storage box or articles of clothing. The method includes collecting radon from the confined area or around a storage box via at least one collector, connecting each of a plurality of radon adsorbers to a corresponding power supply or power source such as a battery, capacitor, fuel cell, etc. diverting, via a plurality of valves, the collected radon or radon daughters through one or more of the plurality of radon adsorbers, and receiving, via a plurality of radon storage units, radon or radon daughters held by the plurality of radon adsorbers for a predetermined period of time.

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.