Abstract: An integrated circuit (IC) chip carrier includes one or more internal metal planes. A dedicated metal plane (DMP) may be formed upon a metal plane dielectric layer. The metal plane dielectric layer may be formed upon a first dielectric layer that is formed upon an IC chip carrier core. The DMP may be formed of the same or different material relative to the material of the wires of the IC chip carrier. The side surfaces of the DMP may be coplanar with associated side surfaces of the IC chip carrier. The DMP may transfer heat from the IC chip horizontally to its side surfaces. A decoupling capacitor is externally connected to the IC chip carrier and is electrically connected to the DMP. By connecting the decoupling capacitor to the DMP, the decoupling capacitor may further reduce inductance and noise within the IC chip system.

Abstract: A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide.

Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.

Abstract: A chemical bath system includes a reactor tank configured to store a chemical bath solution including at least one organic element, and an organics removing chamber assembly. The organics removing chamber assembly includes at least one sub-chamber that delivers the chemical bath solution from a high-pressure section of a bath circuit to a low-pressure section. The organics removing chamber assembly modifies an amount of the at least one organic element as the chemical bath solution flows therethrough. The chemical bath system further includes an analysis/dosing controller. The analysis/dosing controller outputs a control signal that controls the organics removing chamber assembly to modify the amount of the at least one organic element in the chemical bath solution based on a comparison between an actual amount of the at least one organic element in the chemical bath solution and a desired amount of the at least one organic element.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: A semiconductor structure which includes a first semiconductor substrate having a first plurality of copper connectors; a second semiconductor substrate having a second plurality of copper connectors; and a joining structure joining the first plurality of copper connectors to the second plurality of copper connectors, the joining structure including a copper intermetallic mesh having pores filled with silver. There is also a method for joining two semiconductor substrates.

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Abstract: Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Abstract: At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: Electroplating techniques including a system for treating a solution for use in an electroplating application and a method for using the system are provided. The system can have: a gas dispersing portion configured to treat the solution by dispersing a gas into the solution to control a concentration of a predetermined cation of a metal to be electroplated in the electroplating application; a filter portion configured to treat the solution by filtering the solution to remove a quantity of metal residue; and a circulation mechanism configured to divert the solution to one of a plating tool and a combination of the gas dispersing portion and the filter portion based on a result of an analysis of the solution.

Abstract: Plating bath and well structures and methods are described to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing up the reservoir wall. An electroplating apparatus includes a vessel holding a liquid solution including metal plating material and an organic species, and a method of operating an electroplating apparatus. The apparatus is designed with plating bath and structures and methods to stop the organic compounds present in plating reservoir wells or bath solution from rising, i.e., climbing or wicking up the inner surfaces of reservoir walls, and to wash them back down on a continuous or cyclical basis in order to maintain a concentration of organic compounds in the plating solution within upper and lower specification limits.

Abstract: A non alpha controlled plating bath including Tin species and a trace amount of Polonium species is utilized in a plating tool. The plating tool includes a Polonium filter element to remove Polonium species from the plating bath to selectively plate Tin upon a plating cathode. The filter may include a Titanium inner portion surrounding by a stannic oxide exterior. The filter may reduce the Polonium species by having the polonium absorb and then enter within the stannic oxide matrix. The filter may be located within the plating tool reservoir or filter housing. The filter may be fabricated by forming Tin upon a Titanium backbone and converting the Tin to stannic oxide.

Abstract: Electroplating techniques including a system for treating a solution for use in an electroplating application and a method for using the system are provided. The system can have: a gas dispersing portion configured to treat the solution by dispersing a gas into the solution to control a concentration of a predetermined cation of a metal to be electroplated in the electroplating application; a filter portion configured to treat the solution by filtering the solution to remove a quantity of metal residue; and a circulation mechanism configured to divert the solution to one of a plating tool and a combination of the gas dispersing portion and the filter portion based on a result of an analysis of the solution.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.