Abstract: A field-effect transistor (10, FIG. 2) possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.

Abstract: A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.

Abstract: An efficient ESD protection circuit is provided having a resistor (18) disposed between an input pin (12) and the functioning circuitry (22) of an integrated circuit package. A primary switching device (28) is electrically connected between the input pin (12) and a reference voltage pin (14). The resistor (18) comprises an N- well (48) formed within the P- substrate (44) and an N+ diffused reion (50) formed within the N- well (48). A silicided layer (52) is formed over the N+ region (50). The primary switching device (28) is constructed to share the same PN junction (54) utilized by the resistor (18). In constructing the primary switching device (28), a P+ region (70) is formed within the N- well (48). Further, an N+ region (68) is formed within the P- substrate (44). Thus, the primary switching device (40) includes three PN junctions (72, 54, 74) which will conduct at a time prior to, or contemporaneous with, the breakdown of resistor (18).

Abstract: An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BV.sub.CBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground.

Abstract: A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through two separate sets of P and N channel transistors selectively activated by sense clocks. The return transistors are activated for either fast or slow sensing, depending upon the address input. The selected columns are sensed at maximum speed, and non-selected columns which are only being refreshed are sensed at a slower speed. A large return transistor is switched into the circuit only for fast sensing, and other smaller transistors perform the slow sense function with high resistance returns to the supply so peak current is lower. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the 1-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.

Abstract: A semiconductor dynamic read/write memory device having an array of rows and columns of one-transistor cells employs a single-ended sense amplifier connected to a whole column line, rather than a differential sense amplifier having two inputs connected to column line halves. The single-ended sense amplifier includes an input circuit responsive to a selected threshold voltage, and the output of the amplifier is coupled back to the column line. A dummy cell circuit applies a fixed charge to the column line, so the threshold is exceeded if the selected memory cell stores a 1, but not if a zero is stored.

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the I-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.