Patents by Inventor Charvaka Duvvury
Charvaka Duvvury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5986867Abstract: A DRAM output protection circuit (100). A dummy NMOS transistor (116) is connected in parallel with the NMOS output transistor (102). The gate of the dummy transistor (116) is connected through a resistor (122) to ground (108). The resistor 122 value and the gate capacitance (121,127) of the dummy transistor (116) are adjusted to achieve the desired gate matching between the dummy transistor gate (120) and the NMOS output transistor gate (110).Type: GrantFiled: July 22, 1998Date of Patent: November 16, 1999Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Michael D. Chaine
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Patent number: 5982217Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.Type: GrantFiled: February 19, 1998Date of Patent: November 9, 1999Assignee: Texas Instruments IncorporatedInventors: Julian Z. Chen, Larry B. Li, Thomas A. Vrotsos, Charvaka Duvvury
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Patent number: 5977596Abstract: An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.Type: GrantFiled: October 29, 1998Date of Patent: November 2, 1999Assignee: Texas Instruments IncorporatedInventors: Robert Rountree, Charvaka Duvvury, Tatsuroh Maki
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Patent number: 5962898Abstract: A field-effect transistor (10, FIG. 2) possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.Type: GrantFiled: September 12, 1997Date of Patent: October 5, 1999Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5940258Abstract: Protection circuitry (10) for protecting an integrated circuit from an ESD pulse is provided. The protection circuitry (10) includes discharge circuitry (14) on a substrate (11) that discharges an ESD pulse to the integrated circuit to ground (18). The protection circuitry (10) also includes a substrate bias generator (25) that uses a portion of the ESD pulse's energy to bias the substrate (11) of the discharge circuitry (14).Type: GrantFiled: February 5, 1997Date of Patent: August 17, 1999Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5925922Abstract: An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.Type: GrantFiled: August 19, 1993Date of Patent: July 20, 1999Assignee: Texas Instruments IncorporatedInventors: Robert Rountree, Charvaka Duvvury, Tatsuroh Maki
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Patent number: 5907462Abstract: A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).Type: GrantFiled: September 7, 1994Date of Patent: May 25, 1999Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Charvaka Duvvury, Ping Yang, Ekanayake Ajith Amerasekera
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Patent number: 5903032Abstract: A power device having built-in ESD protection. A drain extended NMOS transistor (12) is located in a tank region (18). A silicon controlled rectifier (14) is merged with the drain extended nMOS (12) into the tank region (18). In one aspect of the invention, an anode (28) of the silicon controlled rectifier (14) is connected to a drain (24) of the drain extended nMOS (12) and a cathode (32) of the silicon controlled rectifier (14) is connected to a source (34) of the drain extended nMOS (12).Type: GrantFiled: February 10, 1997Date of Patent: May 11, 1999Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5814865Abstract: An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; andType: GrantFiled: October 31, 1996Date of Patent: September 29, 1998Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Michael D. Chaine
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Patent number: 5796638Abstract: A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance.Type: GrantFiled: June 24, 1996Date of Patent: August 18, 1998Assignees: The Board of Trustees of the University of Illinois, Texas Instruments Incorporated, Hewlett-Packard CompanyInventors: Sung-Mo Steve Kang, Charvaka Duvvury, Carlos Hernando Diaz, Sridhar Ramaswamy
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Patent number: 5714783Abstract: A field-effect transistor possesses improved electrostatic discharge characteristics. The transistor (10), formed in a p-type semiconductor substrate, comprises a gate (16) that forms a channel between two adjacent n-regions (12 and 14). At least one of the n-regions (12) has an n-well (22) below and centered about a contact pad (18). The n-well (22) has a second lower concentration of n-type impurities than either of the n-regions.Type: GrantFiled: April 11, 1994Date of Patent: February 3, 1998Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5648920Abstract: A method and apparatus for deriving total lateral diffusion in MOS transistors includes deriving (40) a DC model. The DC model is then verified (42) with a multifinger transistor. The gate of the multifinger transistor is then isolated (44). Voltage pulses are then applied (46) to the multifinger transistor, and the current attributable to the voltage pulses is measured (48). Using the model, estimates of the total lateral diffusion are adjusted (50) until the modelled current matches the measured current. Finally, the complete and accurate AC/DC model can be used (52) by circuit designers to design various circuits that will operate as designed when implemented.Type: GrantFiled: November 22, 1994Date of Patent: July 15, 1997Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Janet L. Wise
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Patent number: 5604369Abstract: A protection device, circuit, and a method of forming the same. A field oxide drain extended nMOS (FODENMOS) transistor (10) is located in an epitaxial region (16). The FODENMOS transistor (10) comprises a field oxide region (36a) that extends from the source diffused regions (22) to over a portion of the extended drain region (20). A drain diffused region (24) is located within the extended drain region (20). A gate electrode (40) may be located above the field oxide region (36a) if desired. Accordingly, there is no thin oxide interface between the gate electrode (40) and the extended drain region (20) that can lead to low ESD protection.Type: GrantFiled: March 1, 1995Date of Patent: February 18, 1997Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Roy C. Jones, III
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Patent number: 5502317Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.Type: GrantFiled: October 25, 1994Date of Patent: March 26, 1996Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5493133Abstract: A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.Type: GrantFiled: May 17, 1995Date of Patent: February 20, 1996Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Fernando D. Carvajal
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Patent number: 5468667Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).Type: GrantFiled: December 15, 1994Date of Patent: November 21, 1995Assignee: Texas Instruments IncorporatedInventors: Carlos H. Diaz, Charvaka Duvvury, Sung-Mo Kang
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Patent number: 5450267Abstract: An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.Type: GrantFiled: March 31, 1993Date of Patent: September 12, 1995Assignee: Texas Instruments IncorporatedInventors: Carlos H. Diaz, Charvaka Duvvury, Sung-Mo Kang
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Patent number: 5404041Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).Type: GrantFiled: March 31, 1993Date of Patent: April 4, 1995Assignee: Texas Instruments IncorporatedInventors: Carlos H. Diaz, Charvaka Duvvury, Sung-Mo Kang
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Patent number: 5369041Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.Type: GrantFiled: July 14, 1993Date of Patent: November 29, 1994Assignee: Texas Instruments IncorporatedInventor: Charvaka Duvvury
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Patent number: 5343433Abstract: A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.Type: GrantFiled: July 26, 1990Date of Patent: August 30, 1994Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Adin E. Hyslop