Abstract: An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off switch relay (403). The relay is resistively connected by a first resistor (402) to the generator and by a second resistor (404) to the socket (405a) for the device-under-test (406); the relay is operable in a partially ionized ambient. A capacitor (407) is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor (410) is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 k? and 1 M?, preferably about 10 k?, several orders of magnitude greater than the on-resistance of the device-under-test.

Abstract: An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.

Abstract: Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge, wherein the protection device is interdigitated with the component. The invention is applicable to many kinds of components, for example to a noise-decoupling capacitor shaped as an nMOS transistor with thin dielectric, or to an input buffer shaped as an nMOS transistor, or to an antenna shaped as an nMOS transistor. The protection device includes an nMOS transistor. The insulator of the gates, preferably silicon dioxide, is thin and in need of protection against ESD damage. The interdigitation may be configured in one or more planes. Further, the protection device may lie in a single plane spaced apart from the plane defined by the components. The protection device may also partially be merged with the component.

Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.

Abstract: An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off switch relay (403). The relay is resistively connected by a first resistor (402) to the generator and by a second resistor (404) to the socket (405a) for the device-under-test (406); the relay is operable in a partially ionized ambient. A capacitor (407) is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor (410) is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 k? and 1 M?, preferably about 10 k?, several orders of magnitude greater than the on-resistance of the device-under-test.

Abstract: A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: An output circuit for improved ESD protection (FIG. 2) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad 220 and Vdd power supply 240, the pull-up transistor located in a n-well 203 and having at least one gate 210, the gate connected to internal circuitry 230. A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well 203, whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate 251, this gate connected through a resistor 260 to the Vdd power supply 240. The n-well 203 connected to the Vdd power supply 240.

Abstract: A CMOS electrostatic discharge (ESD) protection circuit in a substrate of a first conductivity type, in which a discharge circuit having an MOS transistor in the substrate is operable to discharge the ESD pulse to ground. A drive circuit has a plurality of forward-biased diodes in separate wells of the opposite conductivity type, connected as a string in forward direction. During an ESD event, the diode string uses a portion of the ESD pulse's voltage to enter a high-conductance, conductivity-modulated state, and to provide a large substrate current, and consequently a substrate voltage drop, to turn-on the MOS transistor so that it will ground the ESD pulse.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular semiconductor island (102). Each island contains three parallel regions of the opposite conductivity type: the center region (104) is operable as the transistor drain and the two other regions (103 and 105), abutting the isolations, are operable as transistor sources. Transistor gates (106 and 107) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts (108) are placed on both source regions and the drain region. The source contacts are placed so that the spacing (120) between each contact and its respective isolation is at least twice as large as the spacing (121) between each contact and the gate.

Abstract: An MOS transistor in the surface of a semiconductor substrate (180) of a first conductivity type, which has a grid of isolations (171) in the surface, each grid unit surrounding a rectangular substrate island (102). Each island contains two parallel regions of the opposite conductivity type: one region (174) is operable as the transistor drain and the other region (173) is operable as the transistor drain, each region abutting the isolation. A transistor gate (105) is between the parallel regions, completing the formation of a transistor. Electrical contacts (106) are placed on the source region (173) so that the spacing (120) between each contact and the adjacent isolation is at least twice as large as the spacing (121) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: An integrated circuit protecting an I/O pad 303 against an ESD pulse, the circuit having in the same substrate a discharge sub-circuit 301 and a drive sub-circuit 302, each sub-circuit including an MOS transistor. The circuit comprises a direct connection between the I/O pad 303 and the drain 321 of the drive sub-circuit MOS transistor 306, and further a forward diode 360 inserted between the I/O pad 303 and the drain 311 of the discharge sub-circuit MOS transistor 305 to isolate the junction capacitance of the discharge sub-circuit MOS transistor, whereby electrical noise coupling to the substrate is reduced, RF/analog input signals are improved, and leakage at the I/O pad is reduced.

Abstract: A semiconductor device is designed with a common supply voltage terminal (330). A plurality of standard cells (360-364), each having a plurality of leads (308,326) is connected to the common supply terminal. A plurality of connecting leads (322-324) corresponding to respective standard cells is coupled between at least two leads of the plurality of leads.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly.

Abstract: Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge, wherein the protection device is interdigitated with the component.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (130). A first transistor (106) has a current path coupled to the external terminal and has a first control terminal (114). A second transistor (110) has a current path coupled between the current path of the first transistor and the reference terminal and has a second control terminal (126). A bias circuit comprises a third transistor (116) having a first conductivity type and a fourth transistor (124) having a second conductivity type. The third and fourth transistors have respective current paths coupled in series to the reference terminal. The bias circuit is arranged to produce a first voltage at the first control terminal and a second voltage different from the first voltage at the second control terminal.