Abstract: A virtual reality display includes a display module and an optical module. The display module includes a display, a liquid crystal cell, a first phase retarder, and a polarizing directional lens. The optical module includes a transflective lens, a second phase retarder, a reflective polarizer, and a lens element. The liquid crystal cell is located between the display and the first phase retarder, and the polarizing directional lens is located between the first phase retarder and the transflective lens. The transflective lens is located between the polarizing directional lens and the second phase retarder, and the reflective polarizer is located between the second phase retarder and the lens element.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A circuit carrier includes a substrate, a capacitive electrode layer, a plurality of metal pads and a plurality of bridges, and a plurality of conductive pillars. The capacitive electrode layer formed on a surface of the substrate and includes a plurality of first electrodes and a plurality of second electrodes. At least two of the first electrodes are connected to each other and be arranged across a die-bonding region of the substrate for separating at least two of the second electrodes that partially protrude from the die-bonding region to respectively form extensions. The metal pads and the bridges are formed on another surface of the substrate and are located outside of the die-bonding region. Each of the bridges connects two of the metal pads, and each of the conductive pillars is embedded in the substrate and connects one of the extensions and a corresponding one of metal pads.

Abstract: A level shifter includes a low-level adjustment circuit, a comparator circuit, and a high-level adjustment circuit. The low-level adjustment circuit pulls down a level of one between a first input node and a second input node to a first low supply voltage. The comparator outputs a one having higher level between the level of the first input node and a second low supply voltage to a first output node, wherein the second low supply voltage is higher than the first low supply voltage. The high-level adjustment circuit selectively adjusts the level of the first output node according to the level of the first input node and the level of the second input node to generate an output signal.

Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.

Abstract: An data driven approach to generating synthetic data matrices is presented. By retrieving historical network traffic data, probabilistic models are generated. Optimal distribution families for a set of independent data segments are determined. Applications are tested and performance metrics are determined based on the generated synthetic data matrices.

Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry determines a first parameter having the same value for Cb component and Cr component of the chroma component. The circuitry determines, using the first parameter, a model of entropy coding from a plurality of models. The circuitry performs, using the model, the entropy coding of a second parameter of the CCALF process.

Abstract: An electronic device is provided. The electronic device includes a backlight module, a first liquid-crystal module and a second liquid-crystal module. The first liquid-crystal module is disposed on the backlight module. The second liquid-crystal module is disposed on the first liquid-crystal module. The first liquid-crystal module includes a first liquid-crystal layer, a first polarizer, a second polarizer and a first compensation film. The first polarizer is adjacent to the backlight module compared to the second polarizer. The first liquid-crystal layer is disposed between the first polarizer and the second polarizer and has a first alignment direction. The first compensation film is disposed between the first polarizer or the second polarizer and the first liquid-crystal layer. The first alignment direction is parallel to the transmission axis of the first polarizer or second polarizer.

Abstract: A polymeric nanoparticle that has a size of 30-600 nm in outer diameter and contains a polymeric shell, less than 25 nm in thickness and impermeable to water, one or more aqueous cores enclosed by the polymeric shell, and a bioactive agent encapsulated in each of the one or more aqueous cores. Also disclosed are a method of preparing the polymeric nanoparticle and a method of using it for treating a disease.

Abstract: The techniques described herein relate to ultrasonic welding and related techniques for luggage. In some embodiments, a method of manufacturing a luggage component is provided that includes orienting a first component adjacent to a second component, wherein a first surface of the first component adjacent a second surface of the second component comprises a flat portion with one or more protrusions extending from the flat portion, and applying, via a horn sized to receive the first component, an ultrasonic vibration to melt the one or more protrusions to ultrasonically weld the first component to the second component.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Abstract: There is provided a phase shifter including a first substrate, a second substrate and a dielectric layer between the first substrate and the second substrate, the first substrate includes a first base and a first electrode layer on a side, of the first base, the second substrate includes a second base, a second electrode layer and a reference voltage leading-in end on a side of the second base, the reference voltage leading-in end is coupled to the second electrode layer, one of the first electrode layer and the second electrode layer includes a body structure and branch structures; an orthographic projection of an end of each branch structure away from the body structure on the first base is overlapped with an orthographic projection of the second electrode layer or the first electrode layer on the first base. An antenna is further provided.

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device includes a first semiconductor module, a redistribution layer (RDL) module and a second semiconductor module. The RDL module is disposed on the first semiconductor module. The RDL module includes a plurality of polymer layers and a plurality of vias. The polymer layers are stacked on the first semiconductor module. The vias are disposed within the polymer layers. The second semiconductor module is disposed on the RDL module. A height difference of a top surface of at least one of the polymer layers ranges from 0 um to 1 um; or an angle between a sidewall and a bottom surface of at least one of the vias ranges from 90° to 95°; or a glass transition temperature (Tg) of at least one of the polymer layers is larger than 260° C.

Abstract: A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

Abstract: Systems and methods are directed to email threading based on machine learning determined categories and features. A network system accesses a plurality of emails addressed to a user. The network system then classifies, using a machine learning model, each email into at least one of a plurality of categories. For a category of the plurality of categories, one or more feature values are extracted from each email in the category. Based on the category and the extracted feature values, the network system groups messages having a same feature value in the same category together into a single email thread. Information related to the single email thread is then presented at a client device of the user.

Abstract: The present application discloses a method for fabricating fully depleted silicon-on-insulator PMOS devices, the method includes sequentially forming a polysilicon layer and a hard mask oxide layer on an FDSOI substrate structure; etching to a SiGe layer by using the hard mask oxide layer as a mask to form a PMOS gate stack structure; sequentially depositing a spacer dielectric layer and an epitaxial hard mask; performing photolithography and etching to remove the epitaxial hard mask above the PMOS gate stack and thin the spacer dielectric layer; performing in situ photo resist strip; and etching to remove a residual spacer dielectric layer above the PMOS gate and on its surrounding substrate. The present application can effectively reduce the accumulative loss of a SiGe substrate after the epitaxial hard mask etching, improving the epitaxial growth of PMOS regions and ensuring the performance of the fabricated fully depleted silicon-on-insulator PMOS devices.

Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.

Abstract: A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening.