Abstract: The present application discloses a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes at least one bottom die and a plurality of top dies. The semiconductor structure further includes a redistribution layer (RDL) formed on the at least one bottom die, and a plurality of micro bumps formed on the RDL. The top dies is stacked on the bottom die with their front sides being attached to the micro bumps. The RDL allows communication between a top die and the bottom die and allows the communication between adjacent top dies. The die-stacking structure enables greater computation capability within a smaller area.

Abstract: A method and an apparatus for hybrid training of neural networks for video coding are provided. The method includes: obtaining, in an offline training stage, an offline trained network by training a neural network offline; and refining, in an online training stage, a plurality of neural network layers with constraint on a plurality of parameters of the plurality of neural network layers, where the plurality of neural network layers may include at least one neural network layer in the offline trained network or in a simple neural network connected to the offline trained network.

Abstract: An integrated antenna structure includes a grounding element, a plurality of antenna elements, and a plurality of isolators. The grounding element has an opening. The antenna elements and the isolators are disposed at an outer edge of the grounding element and an edge of the opening. The isolators are located between the antenna elements. Orthogonal projections of the antenna elements and the isolators completely overlap with the grounding element.

Abstract: An electronic apparatus performs a method of decoding video data, including: receiving, from the video signal, a picture frame that includes a first component, and a second component; determining a classifier for a respective sample of the second component using a set of weighted sample values from a first set of samples of the first component associated with the respective sample of the second component, and a second set of samples of the second component associated with the respective sample of the second component, wherein the first set of samples and the second set of samples are collocated, neighbouring, and current samples relative to the respective sample of the second component; determining a sample offset for the respective sample of the second component according to the classifier; and modifying the respective sample of the second component based on the determined sample offset.

Abstract: The present application discloses a semiconductor package and a method for manufacturing a semiconductor package. The semiconductor package includes a plurality of bottom dies and a plurality of top dies stacked on the bottom dies with a first RDL in between, thereby embedding more computation power within one semiconductor package and enabling flexible routing between dies. In addition, the top dies and the bottom dies are stacked in a face-to-face manner so the signal paths between the top dies and the bottom dies can be shortened, and thus, the IR drop of the transmission between dies can be reduced.

Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

Abstract: A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×1015 cm?3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

Abstract: The present application discloses a method for fabricating a conductive layer stack. The method includes forming an intervening layer on an under-layer; and forming a filler layer on the intervening layer, wherein the filler layer comprises tungsten. The intervening layer comprises tungsten silicide and a thickness of the intervening layer is greater than 4.1 nm. The under-layer comprises titanium nitride and comprises a columnar grain structure.

Abstract: An antenna structure and an electronic device are provided. The antenna structure includes a substrate with opposing first and second surfaces, a first radiating element with a first radiating portion and a second radiating portion, a third radiating portion, a feeding portion, and a grounding portion that are connected to the first radiating portion, a second radiating element separate from but coupling with the first radiating portion, a grounding element connected to the grounding portion, and a feeding element. The first radiating portion, the feeding portion, and the grounding portion are disposed on the first surface. The second radiating portion and the third radiating portion are disposed on the second surface. A projected area of the second radiating portion onto the first surface partially overlaps with the feeding portion. A projected area of the third radiating portion onto the first surface partially overlaps with the grounding portion.

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a sensor configured to generate sensor signals indicative of a lifetime of a component of the thin-film deposition system, a characteristic of a thin-film deposited by the thin-film deposition system or a characteristic of a process material that flows into the thin-film deposition system. The system includes a control system configured to adjust a relative location of a top plate of the thin-film deposition system with respect to a location of a wafer in the thin-film deposition system during the thin-film deposition process responsive to the sensor signals.

Abstract: A method of forming a semiconductor structure includes forming a mask layer on a substrate. The mask layer and the substrate include an opening. An isolation structure is formed in the opening. The mask layer is removed. A first conductive layer is formed on the isolation structure and the substrate. A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure. A second conductive layer is formed on the first conductive layer and the isolation structure. A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned.

Abstract: An optical transceiver includes a housing, an optical communication module and a heat dissipation module. The optical communication module includes a substrate, a first optical communication component and a second optical communication component located at opposite sides of the substrate, respectively. The heat dissipation module includes a first heat conductive component and a second heat conductive component disposed on the substrate. The first heat conductive component is spatially spaced apart from the second heat conductive component. The first optical communication component is supported on and in thermal contact with the first heat conductive component. The second optical communication component is mounted on the substrate, and the second optical communication component is in thermal contact with the second heat conductive component through the substrate.

Abstract: In an embodiment, a method includes: forming a first fin and a second fin extending from a semiconductor substrate; depositing a liner layer along a first sidewall of the first fin, a second sidewall of the second fin, and a top surface of the semiconductor substrate, the liner layer formed of silicon oxynitride having a nitrogen concentration; depositing a fill material on the liner layer, the fill material formed of silicon; annealing the liner layer and the fill material, the annealing converting the fill material to silicon oxide, the annealing decreasing the nitrogen concentration of the liner layer; and recessing the liner layer and the fill material to form an isolation region between the first fin and the second fin.

Abstract: A toy gun having embedded magazine includes: a gun body having a bullet feeding slot; a top magazine cover pivotally connected at a top end of the gun body and having an accommodating slot and a first latching structure disposed on one side facing the gun body, the first latching structure is located at one lateral side of the accommodating slot; and a magazine assembly detachably disposed in the accommodating slot and having a main body, the main body has a bullet discharging funnel and a second latching structure, the second latching structure is correspondingly latched with the first latching structure; when the top magazine cover pivotally rotates from top to down to cover on top of the gun body, the bullet discharging funnel is correspondingly disposed in the bullet feeding slot. Accordingly, the magazine is embedded and hidden in the top magazine cover.

Abstract: A strip diverting mechanism includes a negative pressure unit and an air discharge unit. The negative pressure unit and the air discharge unit are arranged opposite each other, and a gap through which a strip passes is formed between the negative pressure unit and the air discharge unit. The negative pressure unit is configured to provide a suction force to the strip and the air discharge unit is configured to provide a repulsive force to the strip, to prevent the strip from contacting the negative pressure unit and the air discharge unit.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.

Abstract: A gas filling docking tray having a carrier substrate includes a base surface, a plurality of guide blocks, a plurality of positioning pins, and at least one pair of nozzles. The guide blocks are at least disposed on two opposite sides of the base surface to define a wafer carrier accommodation area, and each guide block includes a vertical portion substantially perpendicular to the base surface and an inclined portion located above and connected with the vertical portion. A height of an apex of each positioning pin relative to the base surface is greater than a height of an apex of the vertical portion and less than a height of an apex of the inclined portion relative to the base surface.