Patents by Inventor Che Lin

Che Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083555
    Abstract: A waste collection apparatus for collecting waste in water is provided. The waste collection apparatus includes a floating device and a waste collection device coupled to the floating device. The waste collection device includes a fluid ejection element, and the flow out of the fluid ejection element flows toward a space where waste is collected.
    Type: Application
    Filed: May 12, 2023
    Publication date: March 14, 2024
    Inventors: Wei-Chun LIU, Ching-Fu WANG, Cheng-Che HO, Huan-Fu LIN
  • Publication number: 20240085667
    Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: SHENG CHE WU, YU HUNG CHOU, YI HUA LIN, YUAN HUNG SU
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11919284
    Abstract: A rotary seat including a base includes an outer surface, and a composite material layer attached to at least a part of the outer surface. The base also includes a recess for accommodating a turntable and including a first opening on the outer surface. The material of the composite material layer includes fibers and a resin. Therefore, the rotary seat may be more lightweight. A rotary table is also provided and includes the rotary seat, a driving device which drives the rotary seat to rotate, and a turntable which is rotatably disposed in the recess of the base.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 5, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Yung-Tsai Chuo, Yaw-Zen Chang, Jui-Che Lin, Yu-Hsien Ho, Yu Liu
  • Publication number: 20240069431
    Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Che HSIEH, Chien-Cheng Chen, Ping-Hsun Lin, Ta-Cheng Lien, Hsin-Chang Lee
  • Publication number: 20240070582
    Abstract: An apparatus for estimating a fair value of a SPP includes a sunshine simulation system for generating a peak sun hour; a photovoltaic (PV) yield system for measuring a total power loss rate and generating an estimated energy-production-hours database; and a financial pricing system for generating a series of cash flows and discount factors. The financial pricing system computes a series of present values which are the product of the cash flows and the discount factors, and sums up all the present values to obtain an estimated value of the SPP. Since the apparatus for estimating SPP value takes the real power generation condition of the SPP and the real market economic condition into consideration, so that the apparatus can generate a pricing result even closer to the real market.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Guang Teng Renewable Energy Co., Ltd.
    Inventors: An-Hsing CHANG, Ming-Che CHUANG, Shih-Kuei LIN, Che-Yi YIN
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Patent number: 11917923
    Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
  • Patent number: 11913925
    Abstract: A sensing device is provided. The sensing device includes a processing circuit and a multi-sensor integrated single chip. The multi-sensor integrated single chip includes a substrate and a temperature sensor, a pressure sensor, and an environmental sensor disposed on the substrate. The temperature sensor senses temperature. The pressure sensor senses pressure. The environmental sensor senses an environmental state. The processing circuit obtains a first sensed temperature value from the temperature sensor when the environmental sensor does not operate, and it obtains a second sensed temperature value from the temperature sensor when the environmental sensor operates. The processing circuit obtains a sensed pressure value from the pressure sensor. The processing circuit obtains at least one temperature calibration reference of the pressure sensor according to the first and second sensed temperature values and calibrates the sensed pressure value according to the temperature calibration reference.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ying-Che Lo, Yu-Sheng Lin, Po-Jen Su, Ting-Hao Hsiao
  • Publication number: 20240063270
    Abstract: A high electron mobility transistor epitaxial structure includes a substrate, a nucleation layer, a buffer layer, a first nitride layer, a second nitride layer, a channel layer, and a barrier layer. The nucleation layer is located above the substrate. The buffer layer is located above the nucleation layer. The first nitride layer is located above the buffer layer and is in contact with the buffer layer. The second nitride layer is located above the first nitride layer and is in contact with the first nitride layer. A film thickness of the first nitride layer is less than a film thickness of the second nitride layer. The second nitride layer is carbon doped. A carbon concentration of the first nitride layer is less than a carbon concentration of the second nitride layer. The channel layer is located above the second nitride layer.
    Type: Application
    Filed: June 22, 2023
    Publication date: February 22, 2024
    Applicant: GLOBALWAFERS CO., LTD.
    Inventors: JIA-ZHE LIU, HONG-CHE LIN
  • Patent number: 11908516
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 20, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240047278
    Abstract: The invention provides a method for detecting the back surface of a wafer, which comprises providing a wafer and performing a detection step on the back surface of the wafer, wherein the detection step comprises capturing a gray scale map of the back surface of the wafer, finding out at least one defect of the back surface of the wafer according to a deviation of the gray scale map, and transmitting the data of the at least one defect back to a system, and the system performs a judgment step according to the data of the at least one defect.
    Type: Application
    Filed: September 6, 2022
    Publication date: February 8, 2024
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Chen Feng Wang, Ching-Shu Lo, Tsung Che Lin, Sen-Chih Chang, WEN YI TAN
  • Publication number: 20240039149
    Abstract: An electronic device includes a first antenna, a second antenna, and an interference reduction device. The first antenna is arranged at a first position. The second antenna is arranged at a second position. The second position is different from the first position. The interference reduction device is arranged at a third position. The third position is different from the first position and the second position. The interference reduction device includes a structural feature configured to couple an electromagnetic wave and reduce radiation of the electromagnetic wave.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 1, 2024
    Inventors: Yu-Che LIN, Jing NIE
  • Publication number: 20240034244
    Abstract: A bicycle carrier contains: a fixing device, a rotation device, a control device, and a holder. The fixing device includes a connection rod and a positioning seat. The positioning seat has a longitudinal receiving orifice and a lateral receiving orifice. The rotation device includes a casing, a grip, and a grasp space. The control device includes an actuation post, a pull lever, a spring, and an insertion portion. The pull lever has a joining portion and an extension. When the extension is pulled by an external force, the insertion portion removes from the longitudinal receiving orifice and the lateral receiving orifice so that the rotation device is forced to rotate between a horizontal fixing position and a horizontal fixing position reciprocately. When the external force to the extension disappears, the rotation device is located on the vertical fixing position, and the insertion portion is received in the vertical receiving orifice.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventor: Che-Lin Liu
  • Publication number: 20240029423
    Abstract: A method for detecting defect in image is provided. The method obtains a number of original images, determines a first reference image from the original images, and performs a histogram matching on the original images excluding the first reference image according to the first reference image, to obtain a plurality of matched images. The method further generates a synthesized image according to pixel intensities of the matched images and pixel intensities of the first reference image; and uses the synthesized image as a second reference image to perform an image comparison with a test image, to generate a result of defect detection. A related device and a related non-transitory storage medium are also provided.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Inventors: LI-CHE LIN, YEN-YI LIN, CHENG-FENG WANG
  • Patent number: 11879084
    Abstract: In the present disclosure embodiments, a phosphate phosphor including an activation center of trivalent chromium and a light emitting device are provided. The light emitting device includes a light source and the above mentioned phosphate phosphor, such that the phosphate phosphor is excited by the light source and emits a wide spectrum of the infrared light. The light emitting device with wide emission spectrum of the infrared light may be widely applied in detecting devices.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 23, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chun-Che Lin, Chun-Han Lu, Yi-Ting Tsai, Yu-Chun Lee, Tzong-Liang Tsai
  • Patent number: 11873326
    Abstract: The present invention relates to a transgenic CHO cell line in which the BMP receptor gene BMPRIA or BMPRII is knocked out. The BMP type I receptor BMPRIA or BMP type II receptor BMPRII gene which plays an important role in intracellular signal transduction in CHO cells is knocked out to prevent the activation of self concentration control pathway and the signal transduction mediated by BMP in CHO cells, so that the productivity of a target protein to be produced can be improved.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 16, 2024
    Inventors: Gyun-Min Lee, Che Lin Kim
  • Patent number: 11855154
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Publication number: 20230384777
    Abstract: An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to generate a characteristic sequence defining a relationship between at least two manufacturing parameters, and determine a relationship between one or more variables related to the feature and the characteristic sequence. The manufacturing system is further configured to determine a weight based on the determined relationship and apply the weight to the feature. The manufacturing system is further configured to train a machine-learning model in view of the weighted feature.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Jui-Che Lin, Chao-Hsien Lee, Shauh-Teh Juang
  • Publication number: 20230378278
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and 0?y?1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 23, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Chih-Yuan Chuang, Po Jung Lin, Hong Che Lin