Patents by Inventor Chee Hiong Chew
Chee Hiong Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220301876Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG
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Patent number: 11452225Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.Type: GrantFiled: March 29, 2021Date of Patent: September 20, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew, Yushuang Yao
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Publication number: 20220293499Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Asif JAKWANI, Chee Hiong CHEW, Yusheng LIN, Sravan VANAPARTHY, Silnore Tejero SABANDO
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Patent number: 11437304Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.Type: GrantFiled: February 23, 2017Date of Patent: September 6, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Roger Paul Stout, Chee Hiong Chew, Sadamichi Takakusaki, Francis J. Carney
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Publication number: 20220254734Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Yusheng LIN, Swee Har KHOR
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Publication number: 20220246434Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Patent number: 11404277Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: GrantFiled: May 20, 2020Date of Patent: August 2, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Yusheng Lin, Michael J. Seddon, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11404276Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.Type: GrantFiled: May 20, 2020Date of Patent: August 2, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Publication number: 20220238342Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Publication number: 20220208658Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
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Publication number: 20220208635Abstract: A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong LIU, Liangbiao CHEN, Yusheng LIN, Chee Hiong CHEW
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Patent number: 11374373Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.Type: GrantFiled: May 13, 2020Date of Patent: June 28, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Atapol Prajuckamol, Yusheng Lin
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Patent number: 11373939Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.Type: GrantFiled: August 30, 2019Date of Patent: June 28, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang Zhou, Asif Jakwani, Chee Hiong Chew, Yusheng Lin, Sravan Vanaparthy, Silnore Tejero Sabando
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Publication number: 20220199502Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yusheng LIN
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Patent number: 11361970Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.Type: GrantFiled: April 29, 2020Date of Patent: June 14, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Eiji Kurose, Chee Hiong Chew, Soon Wei Wang
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Patent number: 11348796Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: GrantFiled: May 20, 2020Date of Patent: May 31, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11348878Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: GrantFiled: May 28, 2020Date of Patent: May 31, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
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Patent number: 11342237Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.Type: GrantFiled: April 22, 2016Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Patent number: 11342189Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.Type: GrantFiled: August 5, 2020Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Publication number: 20220159853Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Yushuang YAO, Chee Hiong CHEW