Abstract: Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

Abstract: Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

Abstract: A method for plating package leads, in some embodiments, comprises: providing a package having a lead electrically coupled to a tie bar; singulating said lead; electroplating said singulated lead using the tie bar; and singulating said tie bar.

Abstract: A clip for a semiconductor package. Implementations may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

Abstract: A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal.

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Abstract: A method, in some embodiments, comprises: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

Abstract: A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.

Abstract: A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate. The pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate. In implementations the pin includes two rigid portions coupled together only with a coil spring, the spring biasing the rigid portions away from one another when the housing is lowered towards the substrate.

Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.

Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.

Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact s

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.

Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.