Patents by Inventor Chee Hiong Chew

Chee Hiong Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGES WITH DIE INCLUDING CAVITIES AND RELATED METHODS
    Publication number: 20200365408
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • Polymer resin and compression mold chip scale package
    Patent number: 10825786
    Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
  • Semiconductor package system and related methods
    Patent number: 10825748
    Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • FIN FRAME ASSEMBLIES
    Publication number: 20200344905
    Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.
    Type: Application
    Filed: September 30, 2019
    Publication date: October 29, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
  • SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
    Publication number: 20200312749
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har KHOR, Tian Hing LIM, Hui Min LER, Chee Hiong CHEW, Phillip CELAYA
  • REINFORCED SEMICONDUCTOR DIE AND RELATED METHODS
    Publication number: 20200294935
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
  • Semiconductor Package and Related Methods
    Publication number: 20200286865
    Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
    Type: Application
    Filed: January 17, 2020
    Publication date: September 10, 2020
    Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
  • SEMICONDUCTOR PACKAGES WITH THIN DIE AND RELATED METHODS
    Publication number: 20200286735
    Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • BACKMETAL REMOVAL METHODS
    Publication number: 20200286736
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • DIE SIDEWALL COATINGS AND RELATED METHODS
    Publication number: 20200279747
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 3, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Yusheng LIN, Michael J. SEDDON, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • PRESS-FIT PIN FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
    Publication number: 20200274310
    Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong CHEW, Atapol PRAJUCKAMOL, Yusheng LIN
  • Leadless semiconductor packages, leadframes therefor, and methods of making
    Patent number: 10756006
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • DIE SUPPORT STRUCTURES AND RELATED METHODS
    Publication number: 20200258750
    Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface, and a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Michael J. SEDDON, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG, Yusheng LIN
  • SILICON-ON-INSULATOR DIE SUPPORT STRUCTURES AND RELATED METHODS
    Publication number: 20200258751
    Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG
  • Semiconductor devices and methods of making the same
    Patent number: 10727170
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: July 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swee Har Khor, Tian Hing Lim, Hui Min Ler, Chee Hiong Chew, Phillip Celaya
  • Flexible press fit pins for semiconductor packages and related methods
    Patent number: 10720725
    Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 21, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
  • Reinforced semiconductor die and related methods
    Patent number: 10700018
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
  • Press-fit pin for semiconductor packages and related methods
    Patent number: 10693270
    Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 23, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Yusheng Lin
  • SEMICONDUCTOR PACKAGE WITH ELASTIC COUPLER AND RELATED METHODS
    Publication number: 20200194322
    Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Chee Hiong CHEW, Francis J. CARNEY
  • FLEXIBLE PRESS FIT PINS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
    Publication number: 20200176907
    Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL