Patents by Inventor Chee Hiong Chew
Chee Hiong Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200176907Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.Type: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL
-
Publication number: 20200144200Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
-
Publication number: 20200126880Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei WANG, Jin Yoong LIONG, Chee Hiong CHEW, Francis J. CARNEY
-
Publication number: 20200105648Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
-
Patent number: 10607903Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.Type: GrantFiled: April 29, 2019Date of Patent: March 31, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Chee Hiong Chew, Francis J. Carney
-
Publication number: 20200098671Abstract: Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.Type: ApplicationFiled: August 30, 2019Publication date: March 26, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jinchang ZHOU, Asif JAKWANI, Chee Hiong CHEW, Yusheng LIN, Sravan VANAPARTHY, Silnore Tejero SABANDO
-
Patent number: 10559510Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.Type: GrantFiled: November 14, 2017Date of Patent: February 11, 2020Assignee: Semiconductor Components Industries, LLCInventors: Soon Wei Wang, Jin Yoong Liong, Chee Hiong Chew, Francis J. Carney
-
Patent number: 10559905Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: GrantFiled: January 16, 2019Date of Patent: February 11, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
-
Publication number: 20190348342Abstract: Example implementations relate to an electronic module can include a first direct bonded metal (DBM) substrate, a second DBM substrate, a housing member, and a plurality of connection terminals. The first DBM substrate and second DBM substrate can be aligned along a same plane. The housing member can be coupled to the first substrate and the second substrate and the housing member can include a plurality of openings in a surface of the housing member. The plurality of connection terminals can be electrically coupled to at least one of the first DBM substrate and the second DBM substrate, in which a connection terminal from the plurality of terminals can extend through an opening from the plurality of openings of the housing member.Type: ApplicationFiled: May 30, 2018Publication date: November 14, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
-
Publication number: 20190252275Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Chee Hiong CHEW, Francis J. CARNEY
-
Publication number: 20190221532Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.Type: ApplicationFiled: March 25, 2019Publication date: July 18, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Soon Wei WANG, Chee Hiong CHEW, Francis J. CARNEY
-
Patent number: 10319652Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.Type: GrantFiled: June 22, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Chee Hiong Chew, Francis J. Carney
-
Publication number: 20190173215Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: ApplicationFiled: January 16, 2019Publication date: June 6, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL
-
Patent number: 10283466Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.Type: GrantFiled: May 31, 2016Date of Patent: May 7, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
-
Publication number: 20190122967Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. TRUHITTE, Soon Wei WANG, Chee Hiong CHEW
-
Publication number: 20190116669Abstract: One illustrative method embodiment includes: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.Type: ApplicationFiled: December 12, 2018Publication date: April 18, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Atapol PRAJUCKAMOL, Chee Hiong CHEW, Francis J. CARNEY, Yusheng LIN
-
Patent number: 10231340Abstract: A method, in some embodiments, comprises: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.Type: GrantFiled: May 26, 2016Date of Patent: March 12, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Atapol Prajuckamol, Chee Hiong Chew, Francis J. Carney, Yusheng Lin
-
Patent number: 10224655Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: GrantFiled: February 27, 2017Date of Patent: March 5, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
-
Publication number: 20190067143Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.Type: ApplicationFiled: November 14, 2017Publication date: February 28, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei WANG, Jin Yoong LIONG, Chee Hiong CHEW, Francis J. CARNEY
-
Patent number: 10199311Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.Type: GrantFiled: January 25, 2017Date of Patent: February 5, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew