Patents by Inventor Chee-Wee Liu

Chee-Wee Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190165141
    Abstract: A method includes forming a fin structure over a substrate; forming a source/drain structure adjoining the fin structure, in which the source/drain structure includes tin; and exposing the source/drain structure to a boron-containing gas to diffuse boron into the source/drain structure to form a doped region in the source/drain structure.
    Type: Application
    Filed: October 2, 2018
    Publication date: May 30, 2019
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Fang-Liang LU, Pin-Shiang CHEN, Chee-Wee LIU
  • METHOD OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS
    Publication number: 20190157104
    Abstract: A method of forming a semiconductor device includes forming a doped region on a semiconductor substrate, in which the doped region comprises an impurity therein, and performing a laser anneal process to the doped region with a process gas containing a dopant gas, in which the dopant gas and the impurity comprise the same chemical element.
    Type: Application
    Filed: June 1, 2018
    Publication date: May 23, 2019
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chun-Ti LU, Meng-Chin LEE, Fang-Liang LU, Chee-Wee LIU
  • Field effect transistors and methods of forming same
    Patent number: 10290708
    Abstract: Semiconductor devices and methods of forming the same are provided. A first gate electrode layer is formed over a substrate. A first gate dielectric layer is formed over the first gate electrode layer. A first channel layer is formed over the first gate dielectric layer. An isolation layer is formed over the first channel layer. A second channel layer is formed over the isolation layer. A second gate dielectric layer is formed over the second channel layer. The second gate dielectric layer, the second channel layer, the isolation layer and the first channel layer are patterned to form a first opening, the first opening extending through the first gate dielectric layer, the second channel layer and the isolation layer, and into the first channel layer. A first source/drain region is formed in the first opening.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: May 14, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Samuel C. Pan, Chee-Wee Liu, Sheng-Ting Fan
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190131403
    Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU
  • Multi-channel field effect transistors using 2D-material
    Patent number: 10269981
    Abstract: A device includes a semiconductor substrate, a buried oxide over the substrate, a first transition metal dichalcogenide layer over the buried oxide, an insulator over the first transition metal dichalcogenide layer, and a second transition metal dichalcogenide layer over the insulator. A gate dielectric is over the second transition metal dichalcogenide layer, and a gate is over the gate dielectric.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 23, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Pin-Shiang Chen, Hung-Chih Chang, Chee-Wee Liu, Samuel C. Pan
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20190067456
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 28, 2019
    Inventors: I-Hsieh WONG, Samuel C. PAN, Chee-Wee LIU, Huang-Siang LAN, Chung-En TSAI, Fang-Liang LU
  • Semiconductor Device and Method
    Publication number: 20180337032
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Semiconductor device and method
    Patent number: 10109477
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 23, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Method For Non-Resist Nanolithography
    Publication number: 20180248020
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • Through silicon via layout pattern
    Patent number: 10002820
    Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Rong Jan, Che-Yu Yeh, Chee Wee Liu, Chien-Hua Huang, Bing J. Sheu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS THEREOF
    Publication number: 20180166582
    Abstract: A semiconductor device includes a source and a drain and a channel disposed between the source and the drain, a first gate dielectric layer disposed on the channel, a first gate electrode disposed on the first gate dielectric layer, a second gate dielectric layer disposed on the first gate electrode, and a second gate electrode disposed on the second gate dielectric layer. The second gate dielectric layer is made of a ferroelectric material. A first area of a bottom surface of the first gate electrode which is in contact with the first gate dielectric layer where the is greater than a second area of a bottom surface of the second gate dielectric layer which is in contact with the first gate electrode.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 14, 2018
    Inventors: Yu-Hung LIAO, Samuel C. PAN, Sheng-Ting FAN, Min-Hung LEE, Chee-Wee LIU
  • Negative capacitance field effect transistor with charged dielectric material
    Patent number: 9978868
    Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 22, 2018
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Der-Chuan Lai, Samuel C Pan, Yu-Cheng Shen, Min-Hung Lee, Chee-Wee Liu
  • Method for non-resist nanolithography
    Patent number: 9972702
    Abstract: A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: May 15, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, National Taiwan University
    Inventors: Miin-Jang Chen, Kuen-Yu Tsai, Chee-Wee Liu
  • SEMICONDUCTOR DEVICE AND FORMATION THEREOF
    Publication number: 20180102258
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Field effect transistors and methods of forming same
    Patent number: 9923093
    Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 20, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh
  • Semiconductor device and formation thereof
    Patent number: 9847233
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Three-dimensional transistor and methods of manufacturing thereof
    Patent number: 9812558
    Abstract: A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: November 7, 2017
    Assignees: National Taiwan University, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang
  • Three-Dimensional Transistor and Methods of Manufacturing Thereof
    Publication number: 20170194464
    Abstract: A method includes providing a substrate having a mesa, forming a first opening in the mesa, the first opening being surrounded by first inner sidewalls of the mesa exposed by the first opening. The method further includes etching from a first one of the first inner sidewalls of the mesa to form a first vertical recess, the first vertical recess having a wide end and a narrow end, with the narrow end defining a first vertically recessed channel region, and forming a first gate structure over the first vertically recessed channel region.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 6, 2017
    Inventors: Jhih-Yang Yan, Samuel C. Pan, Chee Wee Liu, Hung-Yu Yeh, Da-Zhi Zhang
  • Semiconductor Device and Method
    Publication number: 20170194470
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Application
    Filed: May 10, 2016
    Publication date: July 6, 2017
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Semiconductor device and transistor
    Patent number: 9679893
    Abstract: This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic ID-VG curve but also a better sub-threshold slope.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 13, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Jhih-Yang Yan, Chee-Wee Liu, Der-Chuan Lai