Patents by Inventor Chen An Wu

Chen An Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068124
    Abstract: An apparatus for producing silicon carbide crystal is provided and includes a composite structure formed by a plurality of graphite layers and silicon carbide seed crystals, wherein a density or thickness of each layer of graphite is gradually adjusted to reduce a difference of a thermal expansion coefficient and Young's modulus between the graphite layers and silicon carbide. The composite structure can be stabilized on a top portion or an upper cover of a crucible made of graphite, thereby preventing the silicon carbide crystal from falling off.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 29, 2024
    Inventors: CHIH-LUNG LIN, PO-FEI YANG, CHIE-SHENG LIU, CHUNG-HAO LIN, HSIN-CHEN YEH, HAO-WEN WU
  • Publication number: 20240071538
    Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
  • Patent number: 11915957
    Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Yi-Fam Shiu, Yu-Chen Chen, Yang-Ann Chu, Jiun-Rong Pai
  • Patent number: 11915379
    Abstract: The disclosure provides a display image adjustment method and an augmented reality display device. The display image adjustment method includes the following steps. Received image data is converted to a coordinate system of the augmented reality display device to obtain initial coordinate information. An initial image is provided to an active display region of the augmented reality display device based on the initial coordinate information. The initial coordinate information is adjusted in a virtual adjustment coordinate region to obtain adjusted coordinate information when an adjustment command is received. An adjusted image is provided to the active display region of the augmented reality display device based on the adjusted coordinate information. The display image adjustment method and the augmented reality display device proposed by the disclosure may adjust display content of the AR display device according to user's needs.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Shih-Min Wu, Yi-Fa Wang, Ping-Chen Ma
  • Publication number: 20240054772
    Abstract: Aspects of the disclosure relate to determining a sign type of an unfamiliar sign. The system may include one or more processors. The one or more processors may be configured to receive an image and identify image data corresponding to a traffic sign in the image. The image data corresponding to the traffic sign may be input in a sign type model. The processors may determine that the sign type model was unable to identify a type of the traffic sign and determine one or more attributes of the traffic sign. The one or more attributes of the traffic sign may be compared to known attributes of other traffic signs and based on this comparison, a sign type of the traffic sign may be determined. The vehicle may be controlled in an autonomous driving mode based on the sign type of the traffic sign.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 15, 2024
    Inventors: Zhinan Xu, Maya Kabkab, Chen Wu, Woojong Koh
  • Patent number: 11900586
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240016747
    Abstract: The invention discloses a solid dispersion, a pharmaceutical preparation, a preparation method and an application thereof. The solid dispersion of the invention comprises carriers and active constituents, which is a compound as shown in formula (I) and/or a pharmaceutically acceptable salt thereof; The carrier is “homopolymer and copolymer of N-vinyl lactam” and/or pH-dependent cellulose derivatives. The preparation of the invention comprises the solid dispersion, fillers and disintegrating agents. The solid dispersion of the invention has good dissolution and significantly improves the solubility of effective constituents. The preparation can effectively improve the bioavailability of Bcl-2 inhibitor, has good dissolution and stability, and can improve the safety of a medication.
    Type: Application
    Filed: November 25, 2021
    Publication date: January 18, 2024
    Inventors: Yanqiong LIN, Hualiang XU, Feng XU, Chen WU, Hongtao GUO, Xiaoling HE
  • Patent number: 11877433
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 16, 2024
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 11875477
    Abstract: A method for correcting abnormal point cloud is disclosed. Firstly, receiving a Primitive Point Cloud Data set by an operation unit for dividing a point cloud array into a plurality of sub-point cloud sets and obtaining a plurality of corresponding distribution feature data according to an original vector data of the Primitive Point Cloud Data set. Furthermore, recognizing the sub-point cloud sets according to the corresponding distribution feature data for correcting recognized abnormal point cloud. Thus, when the point cloud array is rendered to a corresponding image, the color defect of the point cloud array will be improved or decreased for obtaining lossless of the corresponding image.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: January 16, 2024
    Assignee: National Applied Research Laboratories
    Inventors: Chih-Wei Wang, Chuan-Lin Lai, Chia-Chen Kuo, I-Chen Wu
  • Patent number: 11865441
    Abstract: The present invention provides a computer-implemented method performed in an electronic device, wherein the computer-implemented method comprises the steps of: determining if an operating system of the electronic device enables a gaming mode; and if it is determined that the operating system of the electronic device enables the gaming mode, controlling a wireless communication module of the electronic device to not perform at least one operation that will decrease throughput of the wireless communication module; and if it is determined that the operating system of the electronic device does not enable the gaming mode, at least one operation that will decrease throughput of the wireless communication module is allowed to be executed by the wireless communication module.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: January 9, 2024
    Assignee: MEDIATEK INC.
    Inventors: Pao-Chen Wu, Yu-Yang Lin, Shiuan-Wen Chen
  • Publication number: 20240006535
    Abstract: A semiconductor structure includes a substrate, a multi-gate FET device disposed over the substrate, a first isolation disposed in the substrate, and a second isolation disposed in the substrate. The multi-gate FET device includes a gate structure and epitaxial source/drain structures disposed at two sides of the gate structure. The first isolation includes a first portion and a second portion over the first portion. A top surface of the second portion is aligned with a top surface of the epitaxial source/drain structures. A width of the second portion is different from a width of the first portion.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Inventors: TZU-GING LIN, CHUN-LIANG LAI, YUN-CHEN WU, SHUN-HUI YANG
  • Patent number: 11863210
    Abstract: Disclosed are systems, devices, modules, methods, and other implementations, including a method for digital predistortion that includes receiving, by a digital predistorter, a first signal that depends on amplitude variations based on an input signal, u, with the variations of the first signal corresponding to time variations in non-linear characteristics of a transmit chain that includes a power amplifier. The method further includes receiving, by the digital predistorter, the input signal u, generating, by the digital predistorter, based at least in part on signals comprising the input signal u and the first signal, a digitally predistorted signal v to mitigate the non-linear behavior of the transmit chain, and providing the predistorted signal v to the transmit chain.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: January 2, 2024
    Assignee: NanoSemi, Inc.
    Inventors: Alexandre Megretski, Zohaib Mahmood, Yan Li, Kevin Chuang, Helen H. Kim, Yu-Chen Wu
  • Publication number: 20230416844
    Abstract: Disclosed herein are methods for detecting methylation in cell-free polynucleotides and methods for detecting the presence of cancer in a subject.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 28, 2023
    Inventors: Regina Santella, Hui Zhou, Hui Chen Wu, Zhiguo Zhang
  • Publication number: 20230402921
    Abstract: An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Applicant: National Taiwan University
    Inventors: Bing-Chen Wu, Tsung-Te Liu
  • Patent number: 11836955
    Abstract: Aspects of the disclosure relate to determining a sign type of an unfamiliar sign. The system may include one or more processors. The one or more processors may be configured to receive an image and identify image data corresponding to a traffic sign in the image. The image data corresponding to the traffic sign may be input in a sign type model. The processors may determine that the sign type model was unable to identify a type of the traffic sign and determine one or more attributes of the traffic sign. The one or more attributes of the traffic sign may be compared to known attributes of other traffic signs and based on this comparison, a sign type of the traffic sign may be determined. The vehicle may be controlled in an autonomous driving mode based on the sign type of the traffic sign.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 5, 2023
    Assignee: Waymo LLC
    Inventors: Zhinan Xu, Maya Kabkab, Chen Wu, Woojong Koh
  • Publication number: 20230387103
    Abstract: A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsien-Feng LIAO, Jian-Hsing LEE, Chieh-Yao CHUANG, Ting-Yu CHANG, Yeh-Ning JOU, Shao-Chang HUANG, Kan-Sen CHEN, Nai-Lun CHENG, Ching-Yi HSU, Yu-Chen WU
  • Publication number: 20230378123
    Abstract: A disclosed system is configured to bond a chip to a substrate and includes a chip processing subsystem that is configured to receive the chip and to expose the chip to a first plasma, and a substrate processing subsystem that is configured to receive the substrate and to expose the substrate to a second plasma. The system further includes a bonding subsystem that is configured to align the chip with the substrate, to force the chip and the substrate into direct mechanical contact with one another by application of a compressive force, and to apply heat to at least one of the chip or the substrate. Application of the compressive force and the heat thereby bonds the chip to the substrate. The first and second plasmas may include H2/N2, H2/Ar, H2/He, NH3/N2, NH3/Ar, or NH3/He and the chip and substrate may be maintained in a low oxygen environment.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: Hui-Min Huang, Kai Jun Zhan, Yi Chen Wu, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 11806909
    Abstract: A biaxially oriented polyester film having the following physical property is provided: when cooled from the molten state at a cooling rate of 20° C./min, an observed recrystallization temperature is 175° C.-200° C. The biaxially oriented polyester film is formed by a thick sheet before bidirectional stretching that is melted and extruded by an extruder and then cooled and formed on a casting roll. The thick sheet before stretching having the following physical property as analyzed by differential scanning calorimetry: a crystallization rate is less than 10%.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 7, 2023
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Wen-Cheng Yang, Chen An Wu, Chun-Cheng Yang, Chia-Yen Hsiao
  • Patent number: 11799012
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: October 24, 2023
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: D1002915
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: October 24, 2023
    Inventor: Chen Wu