Abstract: The present disclosure discloses a structure and a method directed to a semiconductor structure having a resistor structure and a metal-insulator-metal (MIM) capacitor structure formed by a single mask process. The semiconductor structure includes an interconnect structure on a substrate, a first insulating layer on the interconnect structure, first and second conductive plates on the first insulating layer and separated by a second insulating layer, a dielectric layer on the first conductive plate, and a third conductive plate on the dielectric layer. Bottom surfaces of the first and second conductive plates are coplanar.

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

Abstract: A rotor for connection to a stationary member for use in an electric machine is provided. The rotor includes a body defining a center of rotation of the body. The body further defines a first surface extending in a direction generally perpendicular to the center of rotation. The rotor also includes a magnet connected to the body and an adhesive. The adhesive is positioned between the magnet and the body. The adhesive is adapted to assist in securing the magnet to the body. The first surface of the body is adapted to permit removal of material from the body and to assist in balancing the rotor.

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

Abstract: A power converter includes a power converting circuit, an output current control circuit, a high-voltage control circuit, a low-voltage control circuit, and a driving circuit. The power converting circuit receives and converts a HV dc voltage from a HV side to a LV dc voltage to a LV side. The output current control circuit is configured to detect an output current and output a first control signal. The high-voltage control circuit is configured to detect the HV dc voltage and output a second control signal. The low-voltage control circuit is configured to detect the LV dc voltage and output a third control signal selectively according to the LV dc voltage, or the LV dc voltage and the first control signal, or the LV dc voltage and the second control signal. The driving voltage outputs a driving signal to drive the power converting circuit according to the third control signal.

Abstract: A power converter includes a power converting circuit, an output current control circuit, a high-voltage control circuit, a low-voltage control circuit, and a driving circuit. The power converting circuit receives and converts a HCMV dc voltage from a HCMV side to a LA dc voltage to a LA side. The output current control circuit is configured to detect an output current and output a first control signal. The high-voltage control circuit is configured to detect the HCMV dc voltage and output a second control signal. The low-voltage control circuit is configured to detect the LA dc voltage and output a third control signal selectively according to the LA dc voltage, or the LA dc voltage and the first control signal, or the LA dc voltage and the second control signal. The driving voltage outputs a driving signal to drive the power converting circuit according to the third control signal.

Abstract: A power converter includes a power converting circuit, a high-voltage control circuit, a low-voltage control circuit, and a driving circuit. The power converting circuit is configured to receive and convert a HVDC voltage from a high-voltage side to a LVDC voltage to a low-voltage side. The high-voltage control circuit is coupled to the high-voltage side and configured to detect the HVDC voltage and output a first control signal according to the HVDC voltage. The low-voltage control circuit is coupled to the low-voltage side and configured to detect the LVDC voltage and output a second control signal according to the LVDC voltage. The driving voltage is configured to selectively output a driving signal to drive the power converting circuit according to the first or the second control signal.

Abstract: A power converter includes a power converting circuit, a high-voltage control circuit, a low-voltage control circuit, and a driving circuit. The power converting circuit is configured to receive and convert a HVDC voltage from a high-voltage side to a LVDC voltage to a low-voltage side. The high-voltage control circuit is coupled to the high-voltage side and configured to detect the HVDC voltage and output a first control signal according to the HVDC voltage. The low-voltage control circuit is coupled to the low-voltage side and configured to detect the LVDC voltage and output a second control signal according to the LVDC voltage. The driving voltage is configured to selectively output a driving signal to drive the power converting circuit according to the first or the second control signal.

Abstract: A battery power integration apparatus includes a power converter, a battery control module, and a relay. The power converter has an input side and an output side, and the input side is connected to a high-voltage DC voltage. The battery control module includes a relay control circuit and a pre-charge control circuit. The relay is connected to the input side of the power converter and the battery control module. The pre-charge control circuit receives a pre-charge enable signal generated from the power converter to pre-charge the input side of the power converter. The power converter steps down the high-voltage DC voltage to output a low-voltage DC voltage at the output side thereof when the relay control circuit turns on the relay, thus supplying the required power for low-voltage devices inside a hybrid electric vehicle.

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.