Patents by Inventor Chen Chao

Chen Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069806
    Abstract: An integrated circuit includes a logic circuit and an amplifying circuit, in particular a low-noise amplifying circuit. The amplifying circuit includes at least one first transistor. The gate of the first transistor is coupled to a signal input terminal, the source region and the drain region of the first transistor are formed respectively in the well region of the first transistor on both sides of the gate, wherein the source region is coupled to a reference voltage terminal, and the sheet resistance of the source region is lower than that of the drain region. The logic circuit includes at least one second transistor. The sheet resistances of the source region and the drain region of the second transistor are equal.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, Shyh-Chyi Wong, Shu-Yuan Hsu
  • Publication number: 20210202353
    Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Fong JHONG, Chen-Chao WANG, Hung-Chun KUO
  • Patent number: 11050245
    Abstract: A switch apparatus is provided. The switch apparatus includes a signal control switch, a switch circuit, a blocking capacitor and a surge current dissipation circuit. The signal control switch and the switch circuit are respectively controlled by a first control signal and a second control signal to be turned on or off. The blocking capacitor is serially coupled between the switch circuit and a reference voltage end. The surge current dissipation circuit includes a Zener diode circuit or at least one diode circuit, and the at least one diode circuit has one or more diodes coupled in series. The one or more diodes coupled in series are coupled between two ends of the surge current dissipation circuit according to a first polarity direction.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 29, 2021
    Assignee: RichWave Technology Corp.
    Inventor: Chuan-Chen Chao
  • Publication number: 20210175175
    Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fu-Chen CHU, Hung-Chun KUO, Chen-Chao WANG
  • Publication number: 20210135451
    Abstract: An integrated circuit includes a signal pad, receiving an input signal during a normal mode, and receive an ESD signal during an ESD mode; an internal circuit, processing the input signal during the normal mode; a variable impedance circuit, comprising a first end coupled to the signal pad, a second end coupled to the internal circuit, wherein the variable impedance circuit provides a low or high impedance path between the signal pad and the internal circuit during the normal or ESD mode; and a switch circuit, comprising a first end coupled to a control end of the variable impedance circuit, a second end coupled to a reference voltage terminal, and a control end receiving a node voltage, wherein the switch circuit switches the control end of the variable impedance circuit to have a first specific voltage or be electrically floating during the normal or ESD mode.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 6, 2021
    Inventors: Chuan-Chen Chao, Ching-Yao Pai
  • Publication number: 20210104461
    Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Chen-Chao WANG
  • Publication number: 20210042368
    Abstract: Systems, methods, and computer program products for implementing a web crawler platform comprising one or more containerized web crawler programs working in tandem to synergistically index web resources and reduce redundancy experienced by multiple web crawlers independently indexing overlapping web resources. The platform provides a URL namespace, allowing crawlers to register with the platform and create URL endpoints for other crawlers to discover existing crawlers registered to the platform and identify web resources previously indexed. The platform provides crawler to crawler communication and exchanges of data and metadata obtained from web resources that have been previously indexed, allowing for crawlers to share existing data or metadata without having to directly crawl through the web resource.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: CHIH-HSIUNG LIU, Peter Wu, Tzu-Chen Chao, I-CHIEN Lin
  • Patent number: 10916429
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: John Richard Hunt, William T. Chen, Chih-Pin Hung, Chen-Chao Wang
  • Patent number: 10903561
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Chen-Chao Wang, Teck-Chong Lee
  • Patent number: 10903152
    Abstract: A substrate includes: (1) a first patterned conductive layer, the first patterned conductive layer including a pair of first transmission lines adjacent to each other; and (2) a first reference layer above the pair of first transmission lines, the first reference layer defining an opening, wherein the pair of first transmission lines are exposed to the opening.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Hsi Chou, Tsun-Lung Hsieh, Chen-Chao Wang
  • Patent number: 10886263
    Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: William T. Chen, John Richard Hunt, Chih-Pin Hung, Chen-Chao Wang, Chih-Yi Huang
  • Publication number: 20200382884
    Abstract: A hearing training device, is provided, including: a wearable device configured for being worn on the head of a user; a playing device arranged on the wearable device; an acupoint stimulation device, served as a physiotherapy device, comprising a plurality of acupoint stimulation mediums arranged on the wearable device, respectively configured for stimulating a plurality of acupoints on the head of the user and related to hearing, and arranged at the positions of the wearable device corresponding to the acupoints respectively; and a control device being in signal connection with the playing device and storing at least one music file, wherein the control device controls the playing device to play the music file, a beat is formed in an audio track of the music file, and the beat decreases with time, and is fixed until the beat is between 10 Hz and 15 Hz.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 3, 2020
    Inventors: Hui-Shan CHANG, Shin-Da LEE, Chen-Chao HSU, Yao-Yu LIAO
  • Publication number: 20200335858
    Abstract: A semiconductor device package includes a first glass carrier, a package body, a first circuit layer and a first antenna layer. The first circuit layer is disposed on the first surface of the first glass carrier. The first circuit layer has a redistribution layer (RDL). The package body is disposed on the first circuit layer. The package body has an interconnection structure penetrating the package body and is electrically connected to the RDL of the first circuit layer. The first antenna layer is disposed on the second surface of the first glass carrier.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hua CHEN, Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE
  • Publication number: 20200303545
    Abstract: An integrated circuit includes a logic circuit and an amplifying circuit, in particular a low-noise amplifying circuit. The amplifying circuit includes at least one first transistor. The gate of the first transistor is coupled to a signal input terminal, the source region and the drain region of the first transistor are formed respectively in the well region of the first transistor on both sides of the gate, wherein the source region is coupled to a reference voltage terminal, and the sheet resistance of the source region is lower than that of the drain region. The logic circuit includes at least one second transistor. The sheet resistances of the source region and the drain region of the second transistor are equal.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 24, 2020
    Applicant: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, Shyh-Chyi Wong, Shu-Yuan Hsu
  • Publication number: 20200168705
    Abstract: A bipolar transistor includes a collector layer, a base layer on the collector layer, and a first elongated emitter mesa on the base layer having a long side and a short side, wherein the long side is parallel with a first direction, and n separate first emitter-contact structures disposed along the first direction on the first elongated emitter mesa, where n is an integer greater than one.
    Type: Application
    Filed: August 26, 2019
    Publication date: May 28, 2020
    Inventors: Chuan-Chen Chao, Po-Hsiang Yang
  • Publication number: 20200151620
    Abstract: In an approach to detecting the transmission of messages, analyzing said messages, calculating a message risk score and transmitting a warning notification, one or more computer processors detect transmission of a message from a user to a selected recipient. The one or more computer processors extract message information from the detected message. The one or more computer processors retrieve one or more historical conversations between the user and the selected recipient of the detected message. The one or more computer processors determine a risk score corresponding to sending the detected message to the selected recipient based on applying the extracted message information and the retrieved historical conversations to a cognitive model.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 14, 2020
    Inventors: Tzu-Chen Chao, Ching-Chun Liu, Ci-Wei Lan, Tao-Hung Jung, Yu-Siang Chen
  • Patent number: 10636416
    Abstract: A network device is connected to user device and includes a processor and a memory storing executable code executed by the processor. The network device is configured to receive first keyword data and speech data followed by the first keyword data; determine whether the first keyword data corresponds to a first keyword; in response to determining that the first keyword data corresponds to the first keyword, recognize word information from the speech data to generate at least one word recognition result; send the at least one word recognition result through a first communication path to a first network; and in response to determining that the first keyword data corresponds to a second keyword, stop recognizing the word information from the speech data followed by the first keyword data, and send the speech data through a second communication path to the first user device.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: April 28, 2020
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Yee-Lee Shyong, Chen-Chao Chang, Ying-Hui Liang
  • Patent number: 10636752
    Abstract: An integrated circuit and a transmission circuit thereof are provided. The transmission circuit includes an input buffer and a voltage holding circuit. The voltage holding circuit has a first end coupled to the input end of the input buffer, and a second end coupled to a reference voltage end. The voltage holding circuit includes a switch and a diode apparatus coupled in series between the first end and the second end of the voltage holding circuit. The switch is configured to receive a mode signal, and is turned on or cut off according to the mode signal.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 28, 2020
    Assignee: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, E-Jen Lien
  • Publication number: 20200111671
    Abstract: A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG
  • Publication number: 20200083591
    Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 12, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Chi HSIEH, Chen-Chao WANG, Teck-Chong LEE, Chien-Hua CHEN