Patents by Inventor Chen Chu

Chen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250231589
    Abstract: A display includes a display size adjustment module and a flexible display module. The display size adjustment module includes a first element and a second element. The first element includes multiple first ribs arranged at intervals. The second element includes multiple second ribs arranged at intervals and slidably engaged with the first ribs. A size of the display increases as the second element slides away from the first element and decreases as the second element slides toward the first element. The flexible display module is disposed on the display size adjustment module and is bent to a back side of the display size adjustment module. The flexible display module includes a flexible display panel and a flexible support member supporting the flexible display panel. The flexible support member is connected to the second element through at least one of magnetic attraction, electrostatic attraction, or a buckle.
    Type: Application
    Filed: November 19, 2024
    Publication date: July 17, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Yi-Sheng Lin, Chia-Chun Yeh, Chen Chu Tsai
  • Publication number: 20250224648
    Abstract: A capsule type electrophoretic display medium film and a manufacturing method thereof are provided. The capsule type electrophoretic display medium film includes a first stretchable film, a second stretchable film, and a capsule type electrophoretic display medium. The second stretchable film is disposed on the first stretchable film. The capsule type electrophoretic display medium is disposed between the first stretchable film and the second stretchable film and includes multiple capsules. At least one capsule among the capsules presents an elliptical, polygonal, or irregular shape when the capsule type electrophoretic display medium film is in a non-stretched state.
    Type: Application
    Filed: December 27, 2024
    Publication date: July 10, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chao Feng Sung, Chen Chu Tsai, Ming-Huan Yang
  • Patent number: 12334928
    Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and the protection circuit. The protection circuit including a first protection transistor pair and a second protection transistor pair is set between the latch circuit and the input circuit, and is configured to prevent an excessive voltage drop between the input circuit and a pair of output terminals, wherein the pair of output terminals is set between the first and the second protection transistor pairs and used for outputting a pair of output signals. The input circuit includes an input transistor pair coupled between the second protection transistor pair and a low-voltage terminal and configured to operate according to a pair of input signals.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: June 17, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Hui Tsai, Hung-Chen Chu, Yung-Tai Chen
  • Publication number: 20250194250
    Abstract: A transistor backplane structure includes multiple pixel structures and a wire distribution layer. Each of the pixel structures includes a substrate, a transistor disposed on the substrate, and a first insulation layer disposed on the transistor. Multiple conductive vias are disposed in the first insulation layer. The wire distribution layer is disposed on the pixel structures. The stretchable electrode layer at a side of the wire distribution layer away from the pixel structure is connected to a contact of the transistor of the pixel structure through a conductive via in the first insulation layer of the pixel structure to form a pixel electrode.
    Type: Application
    Filed: August 28, 2024
    Publication date: June 12, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chao Feng Sung, Chen Chu Tsai
  • Publication number: 20250174492
    Abstract: An interconnection structure includes a semiconductor substrate, an interlayer dielectric layer that is disposed over the semiconductor substrate, and a metal trench that is formed in the interlayer dielectric layer. The interlayer dielectric layer is formed with an air gap, and the metal trench is disposed over the air gap.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Yun KU, Chia-Chen LEE, Wei-Chen CHU, Chia-Tien WU, Hsin-Ping CHEN
  • Publication number: 20250171643
    Abstract: A polymer and a coating material are provided. The polymer is formed by polymerizing a plurality of monomers. The monomers include a first monomer, a second monomer, and a third monomer. The first monomer is itaconic acid. The second monomer is C1-4 alkyl methacrylate, styrene, isobornyl acrylate, di(C2-4 alkyl) itaconate, or a combination thereof. The third monomer is 2-octylacrylate, C9-12 alkyl acrylate, or a combination thereof. The coating material includes the polymer.
    Type: Application
    Filed: October 11, 2024
    Publication date: May 29, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Ling YEH, Su-Mei CHEN WEI, Chien-Chen CHU, Wei-Cheng TANG, Yi-Che SU
  • Publication number: 20250172884
    Abstract: A reticle pressing device is applied to a reticle box used to accommodate a reticle. The reticle pressing device includes a reticle pressing board, a pressing member, and an adjusting member. The pressing member is disposed on the reticle pressing board. The pressing member includes a pushing portion. The pushing portion pushes the reticle pressing board correspondingly according to movement range of the pressing member toward the reticle pressing board, so that the reticle pressing board moves laterally relative to the pressing member. The adjusting member is disposed in the reticle pressing board through the pressing member. The adjusting member is used to adjust the movement range of the pressing member, so that the pushing portion pushes toward the reticle pressing board until the reticle is fixed, or adjusts the pushing portion of the pressing member to move away from the reticle and release pushing force.
    Type: Application
    Filed: May 30, 2024
    Publication date: May 29, 2025
    Applicant: GUDENG PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ming-Chien CHIU, Yung-Chin PAN, Yu-Chen CHU, Chi-Chuan HUANG
  • Patent number: 12300600
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee
  • Publication number: 20250149437
    Abstract: An interconnection structure includes a semiconductor substrate that is formed with a first metal trench and a second metal trench, a first metal via, a second metal via, a third metal trench and a fourth metal trench. The first metal via is disposed over and connected to the first metal trench. The second metal via is disposed over and connected to the second metal trench. The third metal trench is disposed over and connected to the first metal via. The fourth metal trench that is disposed over and connected to the second metal via. A thickness of the third metal trench is different from a thickness of the fourth metal trench.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Chen LEE, Chia-Tien WU
  • Patent number: 12294361
    Abstract: An output stage of an Ethernet transmitter is provided. The output stage is coupled to a resistor and includes a first output terminal, a second output terminal, a first transistor, and a first transistor group. The resistor is coupled between the first output terminal and the second output terminal. The first transistor has a first source, a first drain, and a first gate, the first source being coupled to a first reference voltage and the first drain being coupled to the second output terminal. The first transistor group is coupled to the first reference voltage and the first output terminal. The first transistor group includes multiple transistors which are connected in parallel, and the magnitude of the current flowing to the first output terminal is related to the number of transistors that are turned on.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: May 6, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Hui Tsai, Hung-Chen Chu, Yung-Tai Chen
  • Publication number: 20250140683
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Pu CHOU, Chia-Tien WU, Hsin-Ping CHEN, Wei-Chen CHU
  • Publication number: 20250125148
    Abstract: A method of semiconductor fabrication includes forming a plurality of mandrel recesses in a mandrel layer over a hard mask layer, performing a first patterning process on a spacer layer that is deposited over the mandrel layer to form a first opening pattern, performing a second patterning process to etch portions of the mandrel layer to form a second opening pattern, performing a third patterning process to form a third opening pattern in the hard mask layer based on the first opening pattern and the second opening pattern, and forming, through the hard mask layer, metal lines that are in a semiconductor layer under the hard mask layer and that are arranged in a pattern which corresponds to the third opening pattern.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chen LEE, Chia-Tien WU, Wei-Chen CHU, Hsi-Wen TIEN, Wei-Cheng TZENG, Ching-Yu HUANG, Wei-Cheng LIN, Ken-Hsien HSIEH
  • Publication number: 20250118598
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Shao-Kuan LEE, Kuang-Wei YANG, Gary HSU WEI LIU, Yen-Ju WU, Jing-Ting SU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250112088
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Yen Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Jing Ting SU, Kai-Fang CHENG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Publication number: 20250079298
    Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Inventors: Pokuan Ho, Chia-Tien Wu, Hsin-Ping Chen, Wei-Chen Chu
  • Publication number: 20250079295
    Abstract: An interconnection structure includes a substrate, a first dielectric layer over the substrate, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, and a hyper via. The first dielectric layer is formed with a first metal trench. The second dielectric layer is formed with a metal plate and a connection via. The connection via interconnects the metal plate and the first metal trench. The hyper via penetrates the third dielectric layer and is connected to the metal plate. The hyper via is at least 1.5 times wider than the connection via.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chen LEE, Chia-Tien WU, Wei-Chen CHU
  • Patent number: 12243901
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 4, 2025
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 12243448
    Abstract: A flexible display device includes a supporting layer and a flexible display panel. The supporting layer has two non-folding regions and a folding region between the two non-folding regions. The folding region has a central region and two edge regions. Each of the edge regions is located between one of the two non-folding regions and the central region, and open porosities of the two edge regions are different from an open porosity of the central region. The flexible display panel is located on the supporting layer.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 4, 2025
    Assignee: E Ink Holdings Inc.
    Inventors: Kuo Chang Lee, Yi-Sheng Lin, Chen-Chu Tsai
  • Patent number: 12230534
    Abstract: A semiconductor device includes a conductive line and a conductive via contacting the conductive line. A first dielectric material contacts a first sidewall surface of the conductive via. A second dielectric material contacts a second sidewall surface of the conductive via. The first dielectric material includes a first material composition, and the second dielectric material includes a second material composition different than the first material composition.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Chih Wang, Chia-Tien Wu, Hsin-Ping Chen, Shau-Lin Shue
  • Publication number: 20250054811
    Abstract: A method for manufacturing a semiconductor structure includes: forming a patterned first layer which is made of a first electrically conductive material, and which includes first lines, second lines, and a connection portion disposed on a part of one of the first lines, the first lines having a height lower than a height of the second lines; forming a first via which is connected to an upper surface of the connection portion, the first via having a height above the connection portion; and forming a second via which is connected to an upper surface of one of the second lines, the second via having a height that is the same as the height of the first via above the connection portion.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chen CHU, Chia-Tien WU, Chuan-Pu CHOU, Hsin-Ping CHEN