Abstract: An optoelectronic device and a manufacturing method thereof are provided. The optoelectronic device includes a substrate, light emitting chips disposed on the substrate and electrically connected to the substrate, a first annular structure disposed on the substrate and around the light emitting chips, a first wavelength conversion layer disposed in the first annular structure and covering the light emitting chips, a second annular structure disposed on the substrate and around the light emitting chips and further being in contact with the first annular structure, and a second wavelength conversion layer disposed in the second annular structure and covering the first wavelength conversion layer and the light emitting chips. Wavelength conversion substances contained in the first wavelength conversion layer and the second wavelength conversion layer respectively are different in material. Therefore, the optoelectronic device can achieve improved uniformity of luminescence as well as light output quality.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

Abstract: A fan control system applied to N fans inside a computer system is disclosed, comprising: a main microphone, a control circuitry, a wave generation circuitry and a number N of fan controllers. The control circuitry calculates a basic frequency value according to a temperature inside the computer system, and continuously updates a parameter by any known optimization algorithm according to a main audio signal from the main microphone. The wave generation circuitry generates N square waves according to the basic frequency value and the parameter. The N fan controllers respectively form and transmit N modulation signals to the N fans according to the N square waves and N tachometric signals from the N fans. The parameter is one of a frequency variation and a set of phase differences, and the N square waves have the same frequency.

Abstract: The present application reveals a system for computing and a method for arranging nodes thereof, which is applied for a remote host connected with a plurality of computing nodes divided to a plurality of first nodes and second nodes due to a first computing mode and a second computing mode. After the remote host receives a job, the remote host evaluates the computing nodes in accordance with the job and a corresponding priority weight parameter to generate a job beginning data to set the first nodes or the second nodes and to proceed the job. While setting the first or the second nodes, the remote host provides the corresponding system image to the corresponding nodes; while the first or the second nodes are full in resource arrangement, the empty nodes will be converted to the supplement nodes with the corresponding system image from the remote host.

Abstract: A biometric verification device includes a backlight module, a photodetector, a switching element, and at least one collimation structure. The photodetector is disposed on the backlight module. The switching element is disposed on the backlight module and electrically connected with the photodetector. The at least one collimation structure is disposed on the backlight module and has a first pinhole and a second pinhole, The horizontal projections of the first pinhole and the second pinhole on the backlight module do not overlap with the horizontal projection of the photodetector on the backlight module.

Abstract: There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.

Abstract: A display device includes a driving substrate, an electronic ink layer, and a conductive barrier layer. The electronic ink layer is located on the driving substrate. The conductive barrier layer is located on the electronic ink layer, the conductive barrier layer includes a conductive layer and a base layer, the conductive layer is located between the base layer and the electronic ink layer, and the conductive layer is separated from the electronic ink layer.

Abstract: A system, method, and machine-readable storage medium for restoring a data object for a specified active time period are provided. In some embodiments, the method includes receiving, by a storage device from a client, a request specifying an active time period for a data object to remain stored on an accessible tier. The method also includes determining, by the storage device, that the active time period has elapsed. The method further includes responsive to a determination that the active time period has elapsed, sending, by the storage device, a request to a server storing the data object to move the data object from the accessible tier to an archive tier. Data objects that are stored on the accessible tier are accessible by the client, and data objects that are stored on the archive tier are inaccessible by the client.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The conductive line has a barrier region surrounding an inner portion of the conductive line, and the barrier region has a greater dopant concentration than the inner portion. The semiconductor device structure also includes a conductive via on the conductive line. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate. The dielectric layer surrounds the conductive line and the conductive via.

Abstract: A fingerprint sensing module, including a photosensitive element layer and a color filter layer, is provided. The photosensitive element layer has multiple photosensitive regions, and includes a substrate and multiple photosensitive pixels. The photosensitive pixels have multiple photosensitive patterns overlapping the photosensitive regions. The photosensitive pixels include multiple first photosensitive pixels overlapping multiple first photosensitive regions and multiple second photosensitive pixels overlapping multiple second photosensitive regions. A percentage value of a number of the second photosensitive pixels to a number of the photosensitive pixels is less than 30%. An orthographic projection area of each of the first photosensitive regions is different from an orthographic projection area of each of the second photosensitive regions.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: A flexible display device includes a supporting layer and a flexible display panel. The supporting layer has two non-folding regions and a folding region between the two non-folding regions. The folding region has a central region and two edge regions. Each of the edge regions is located between one of the two non-folding regions and the central region, and open porosities of the two edge regions are different from an open porosity of the central region. The flexible display panel is located on the supporting layer.

Abstract: A hearing device is disclosed, comprising a main microphone, M auxiliary microphones, a transform circuit, a processor, a memory and a post-processing circuit. The transform circuit transforms first sample values in current frames of a main audio signal and M auxiliary audio signals from the microphones into a main and M auxiliary spectral representations. The memory includes instructions to be executed by the processor to perform operations comprising: performing ANC over the first sample values using an end-to-end neural network to generate second sample values; and, performing audio signal processing over the main and the M auxiliary spectral representations using the end-to-end neural network to generate a compensation mask. The post-processing circuit modifies the main spectral representation with the compensation mask to generate a compensated spectral representation, and generates an output audio signal according to the second sample values and the compensated spectral representation.

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: A system, method, and machine-readable storage medium for restoring a data object for a specified active time period are provided. In some embodiments, the method includes receiving, by a storage device from a client, a request specifying an active time period for a data object to remain stored on an accessible tier. The method also includes determining, by the storage device, that the active time period has elapsed. The method further includes responsive to a determination that the active time period has elapsed, sending, by the storage device, a request to a server storing the data object to move the data object from the accessible tier to an archive tier. Data objects that are stored on the accessible tier are accessible by the client, and data objects that are stored on the archive tier are inaccessible by the client.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a conductive layer over a semiconductor substrate and forming a sacrificial layer over the conductive layer. The method also includes partially removing the sacrificial layer to form a first dummy element. The method further includes etching the conductive layer with the first dummy element as an etching mask to form a conductive line. In addition, the method includes partially removing the first dummy element to form a second dummy element over the conductive line. The method also includes forming a dielectric layer to surround the conductive line and the second dummy element and removing the second dummy element to form a via hole exposing the conductive line. The method further includes forming a conductive via in the via hole.

Abstract: A video conferencing system is provided, which includes at least one camera device, a microphone array device, a sound output device, and a processor. The processor is configured to: receive multiple image signals converted by an image shot by the at least one camera device, and receive multiple voice signals converted from multiple voices captured from the microphone array device; and select at least one sound source signal corresponding to multiple personnel positions from the multiple sound signals according to the image signal and the multiple voice signals, so as to transmit at least one sound source signal corresponding to the multiple personnel positions to the sound output device, where the sound output device converts at least one sound source signal into sound for play. In addition, a video conferencing method is also disclosed herein.