Abstract: The present disclosure provides a display substrate, in which power lines and compensation detection lines are alternately arranged at intervals, and two columns of pixel driving circuits extending along a second direction are arranged between any one of the power lines and one adjacent compensation detection line; and for any one of a plurality of pixel driving circuits, a power input terminal of the pixel driving circuit is electrically connected to the power line closest to the pixel driving circuit, and a compensation detection signal terminal of the pixel driving circuit is electrically connected to the compensation detection line closest to the pixel driving circuit. The present disclosure further provides a display device.

Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.

Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

Abstract: A method includes forming a first waveguide over a substrate; forming a first layer of low-dimensional material on the first waveguide; forming a first layer of dielectric material over the first layer of low-dimensional material; forming a second layer of low dimensional material on the first layer of dielectric material; and forming a first conductive contact that electrically contacts the first layer of low-dimensional material and a second conductive contact that electrically contacts the second layer of low-dimensional material.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

Abstract: An image sensor chip with depth information is provided. The image sensor chip includes an SPAD array, a time-to-digital converter module, a storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units, and each of the image sensor units includes a plurality of SPAD units and a decision circuit, wherein each of the SPAD units outputs a photon detection result within a scan period, and the decision circuit generates an image-sensing signal based on the photon detection results. The time-to-digital converter module generates a plurality of first time data in response to the image-sensing signals. The storage circuit stores the first time data temporarily. The data processing unit reads the first time data from the storage circuit and generates a plurality of second time data in response to the first time data.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A light-emitting touch panel includes a circuit board, a plurality of light-emitting elements, a shading plate and a cover plate. The light emitting element has a first height in a first direction. The shading plate has a plurality of spacing regions corresponding to the light emitting elements, respectively. A first width is provided between two partition walls of each spacing region in a second direction. Each partition wall has a second height in the first direction, and the second height is greater than the first height. The cover plate has a light-transmitting region, the light emitted by the light-emitting elements passes through the light-transmitting region, and a bright region is formed on the top surface of the cover plate away from the shading plate, wherein a second width of the bright region in the second direction is related to the second height and the first width.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: There is provided a display substrate and a display device. The display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer which are stacked; wherein the metal oxide layer comprises a first pattern, a second pattern and a capacitance pattern, the first metal layer comprises a first electrode plate, there is at least a first overlapping region between the first electrode plate and the capacitance pattern to form a first storage capacitor, the second metal layer comprises a second electrode plate, there is at least a second overlapping region between the second electrode plate on the base substrate and the capacitance pattern to form a second storage capacitor, and the first electrode plate and the second electrode plate have same potential.

Abstract: A keyboard device includes plural keycaps, a base plate, plural connecting elements and a circuit board. The plural connecting elements are connected with the respective keycaps and the base plate. The circuit board is located over the base plate. The circuit board includes plural membrane switches and plural first capacitance sensing units. When one of the first capacitance sensing units detects an approaching conductor or detects a motion of the conductor, a driving signal is generated or a control signal is outputted.

Abstract: A trimming method is provided. The trimming method includes the following steps. A first wafer including a substrate and a device layer over a first side of the substrate is provided. The first wafer is bonded to a second wafer with the first side of the substrate facing toward the second wafer. An edge trimming process is performed to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction.

Abstract: The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.

Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.